The template for VLSI project
☆26May 10, 2019Updated 6 years ago
Alternatives and similar repositories for vlsi_project
Users that are interested in vlsi_project are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- This is a tutorial on standard digital design flow☆84May 24, 2021Updated 4 years ago
- This is a project integrating HLS IP and CortexA9 on Zynq. This CPU-FPGA project, for a Matrix Multiplication Dataflow, is implemented wi…☆21Sep 3, 2019Updated 6 years ago
- All the projects and assignments done as part of VLSI course.☆20Sep 23, 2020Updated 5 years ago
- RTL Synthesis for Fast Arithmetic circuits like Booth encoded Multipliers, Carry Save Adders, Fixed-Point and Floating-Point conversions,…☆21Nov 26, 2018Updated 7 years ago
- This paper presents design of UART module for serial communication used for short-distance, low speed and exchange of data between comput…☆15Mar 30, 2022Updated 4 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- The template for VLSI project☆29Mar 3, 2023Updated 3 years ago
- This is this VLSI designing Project. This Project is created in Cadence Virtuoso. See the PDF for Pre-Post layout results and other detai…☆40Mar 22, 2019Updated 7 years ago
- UCSD ECE277 GPU Programming coursework: GPU-accelerated reinforcement learning on CUDA C with Nsight System☆14Aug 17, 2021Updated 4 years ago
- Submission template for Tiny Tapeout IHP shuttles - Verilog HDL Projects☆33Mar 14, 2026Updated last month
- Chisel3 implementation of IEEE-754 compliant floating point data type (logic & representation)☆11Dec 16, 2019Updated 6 years ago
- To design test bench of the APB protocol☆20Dec 30, 2020Updated 5 years ago
- Systolic Three Matrix Multiplier for Graph Convolutional Networks using High Level Synthesis☆23Jul 29, 2022Updated 3 years ago
- [DAC2024] Explainable Fuzzy Neural Network with Multi-Fidelity Reinforcement Learning for Micro-Architecture Design Space Exploration☆10Oct 31, 2024Updated last year
- A customized RISCV core made using verilog☆18Mar 4, 2021Updated 5 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- the APAP image stitching algorithm in python☆16Sep 29, 2022Updated 3 years ago
- ☆16Sep 26, 2022Updated 3 years ago
- Fast and Flexible FPGA development using Hierarchical Partial Reconfiguration (FPT 2022)☆15Mar 21, 2024Updated 2 years ago
- Memory Simulator and Optimizer☆22Oct 23, 2019Updated 6 years ago
- Personal mirror for adv_debug_sys☆11Aug 23, 2011Updated 14 years ago
- This is a open source project from UVM Community and it is based on an Ethernet Switch System-on-Chip (SoC).☆15May 16, 2021Updated 4 years ago
- ☆13Jan 28, 2026Updated 3 months ago
- General Purpose IO with APB4 interface☆16May 10, 2024Updated last year
- Built a test environment using UVM Methodology to verify APB Protocol.☆16Feb 6, 2019Updated 7 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- 基于RISC_V32I指令集架构的五级流水CPU☆15Sep 30, 2019Updated 6 years ago
- DTMF Receiver: Logic Synthesis and Physical Design using genus and innovus in 90nm process node☆15Dec 1, 2023Updated 2 years ago
- (under construction) Experimental circuit design for FPGA based PCIe accelerator board providing emulated NVMe/PCIe device that its read/…☆28Feb 7, 2023Updated 3 years ago
- ☆16Sep 25, 2020Updated 5 years ago
- ☆37Sep 19, 2025Updated 7 months ago
- APB Timer Unit☆14Oct 30, 2025Updated 5 months ago
- An implementation of the paper "Dynamic Locomotion in the MIT Cheetah 3 Through Convex Model-Predictive Control" into Quad-SDK☆19Jun 29, 2024Updated last year
- Cortex-M0 DesignStart Wrapper☆24Aug 11, 2019Updated 6 years ago
- Cryptography accelerator ASIC (for AES128/AES256 and SHA256) using Skywater 130nm process node (build-environment repo).☆11Jan 13, 2021Updated 5 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- example code for the logi-boards from pong chu HDL book☆30Sep 4, 2015Updated 10 years ago
- Multi-path UDP protocol - an example implementation☆10Jul 6, 2015Updated 10 years ago
- DLB (Deep Learning Blocks) as a part of DPU (Deep Learning Processing Unit) is a collection of synthesizable Verilog modules for deep lea…☆23Aug 13, 2025Updated 8 months ago
- ☆13Feb 13, 2021Updated 5 years ago
- Julia package for computing Hamilton-Jacobi Reachability of optimal 2-player (control/disturbance) differential games via Hopf optimizati…☆23Aug 14, 2025Updated 8 months ago
- Dense optical flow toolbox (from C.Liu)☆18Jun 14, 2012Updated 13 years ago
- RISC V core implementation using Verilog.☆30Mar 27, 2021Updated 5 years ago