The template for VLSI project
☆25May 10, 2019Updated 6 years ago
Alternatives and similar repositories for vlsi_project
Users that are interested in vlsi_project are comparing it to the libraries listed below
Sorting:
- This paper presents design of UART module for serial communication used for short-distance, low speed and exchange of data between comput…☆15Mar 30, 2022Updated 3 years ago
- Chisel3 implementation of IEEE-754 compliant floating point data type (logic & representation)☆11Dec 16, 2019Updated 6 years ago
- To design test bench of the APB protocol☆18Dec 30, 2020Updated 5 years ago
- This is a project integrating HLS IP and CortexA9 on Zynq. This CPU-FPGA project, for a Matrix Multiplication Dataflow, is implemented wi…☆20Sep 3, 2019Updated 6 years ago
- Memory Simulator and Optimizer☆22Oct 23, 2019Updated 6 years ago
- Systolic Three Matrix Multiplier for Graph Convolutional Networks using High Level Synthesis☆23Jul 29, 2022Updated 3 years ago
- All the projects and assignments done as part of VLSI course.☆20Sep 23, 2020Updated 5 years ago
- ☆12May 21, 2024Updated last year
- This is this VLSI designing Project. This Project is created in Cadence Virtuoso. See the PDF for Pre-Post layout results and other detai…☆37Mar 22, 2019Updated 6 years ago
- Parks-McClellan algorithm for FIR filter design☆34Aug 28, 2024Updated last year
- ☆13Jan 28, 2026Updated last month
- ☆10Oct 23, 2016Updated 9 years ago
- ☆11Apr 3, 2017Updated 8 years ago
- DTMF Receiver: Logic Synthesis and Physical Design using genus and innovus in 90nm process node☆14Dec 1, 2023Updated 2 years ago
- ☆11Oct 10, 2018Updated 7 years ago
- mirror of https://git.elphel.com/Elphel/eddr3☆42Oct 16, 2017Updated 8 years ago
- Sargon Chess for CP/M☆11May 12, 2021Updated 4 years ago
- Personal mirror for adv_debug_sys☆11Aug 23, 2011Updated 14 years ago
- A tool for modeling FSMs by VHDL or Verilog☆11Updated this week
- ☆10Mar 18, 2020Updated 5 years ago
- Main repo of the OOP class☆11Oct 16, 2017Updated 8 years ago
- A simple tool to demonstrate the physical design steps of VLSI Design Flow.☆10Dec 13, 2020Updated 5 years ago
- Portal for 2024 SIT batch being mentored at the Advnaced VLSI Lab.☆11Apr 9, 2023Updated 2 years ago
- Alpha64 R10000 Two-Way Superscalar Processor☆11May 6, 2019Updated 6 years ago
- Audio libs for load and play some audio files☆10Jan 3, 2021Updated 5 years ago
- This is a open source project from UVM Community and it is based on an Ethernet Switch System-on-Chip (SoC).☆15May 16, 2021Updated 4 years ago
- FPGA Labs for EECS 151/251A (Fall 2021)☆11Oct 20, 2021Updated 4 years ago
- ☆12May 29, 2020Updated 5 years ago
- All switching software as well as control software for a physically and emulated capable network coding switch. FPGA Acceleration added .…☆10Nov 19, 2019Updated 6 years ago
- The Repository contains the code of various Digital Circuits☆12Aug 7, 2023Updated 2 years ago
- Windows 2000 Source Code☆11Aug 3, 2024Updated last year
- This is Max's blog, something interesting in it.☆13Jan 1, 2023Updated 3 years ago
- Verilog SDR SDRAM controller for FPGA Xilinx and Lattice☆17Jan 3, 2021Updated 5 years ago
- Mirror of NetBSD sources useful with rump kernels☆13Mar 23, 2017Updated 8 years ago
- SATA sniffing☆15Jul 28, 2022Updated 3 years ago
- Dual-core 16-bit RISC processor☆12Jul 21, 2024Updated last year
- A vhdl package for reading and writing bitmap files.☆11Jan 9, 2018Updated 8 years ago
- Multi-path UDP protocol - an example implementation☆10Jul 6, 2015Updated 10 years ago
- APB Timer Unit☆13Oct 30, 2025Updated 4 months ago