zhujingyang520 / vlsi_projectLinks
The template for VLSI project
☆21Updated 6 years ago
Alternatives and similar repositories for vlsi_project
Users that are interested in vlsi_project are comparing it to the libraries listed below
Sorting:
- RTL code of some arbitration algorithm☆14Updated 6 years ago
- AXI3 Bus Functional Models (Initiator & Target)☆29Updated 2 years ago
- HLS for Networks-on-Chip☆36Updated 4 years ago
- Xilinx AXI VIP example of use☆42Updated 4 years ago
- The memory model was leveraged from micron.☆23Updated 7 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆53Updated 4 years ago
- General Purpose AXI Direct Memory Access☆59Updated last year
- Binary Single Precision Floating-point Fused Multiply-Add Unit Design (Verilog HDL)☆21Updated 12 years ago
- Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.☆22Updated last year
- IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system☆20Updated 3 weeks ago
- The Verilog source code for DRUM approximate multiplier.☆31Updated 2 years ago
- SoC Based on ARM Cortex-M3☆33Updated 4 months ago
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆45Updated last year
- ☆21Updated 5 years ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆14Updated last year
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆59Updated last month
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆69Updated 9 months ago
- ☆66Updated 4 years ago
- Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.☆34Updated last year
- ☆29Updated 5 years ago
- Simple single-port AXI memory interface☆46Updated last year
- ☆27Updated 5 years ago
- ☆21Updated 5 years ago
- APB Logic☆19Updated last month
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆42Updated 2 years ago
- ☆29Updated last month
- A simple, scalable, source-synchronous, all-digital DDR link☆30Updated 3 months ago
- ☆14Updated 2 years ago
- A Verilog implementation of a processor cache.☆28Updated 7 years ago
- Synopsys Design compiler, VCS and Tetra-MAX☆19Updated 7 years ago