zhujingyang520 / vlsi_project
The template for VLSI project
☆15Updated 5 years ago
Related projects ⓘ
Alternatives and complementary repositories for vlsi_project
- Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.☆13Updated 3 months ago
- RTL code of some arbitration algorithm☆12Updated 5 years ago
- Binary Single Precision Floating-point Fused Multiply-Add Unit Design (Verilog HDL)☆17Updated 11 years ago
- Simple demo showing how to use the ping pong FIFO☆13Updated 8 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆44Updated 3 years ago
- This is a project integrating HLS IP and CortexA9 on Zynq. This CPU-FPGA project, for a Matrix Multiplication Dataflow, is implemented wi…☆19Updated 5 years ago
- SRAM☆20Updated 4 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆48Updated 5 months ago
- CNN accelerator using NoC architecture☆15Updated 5 years ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆29Updated 8 years ago
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆18Updated 6 years ago
- The Verilog source code for DRUM approximate multiplier.☆28Updated last year
- IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system☆18Updated last month
- Xilinx AXI VIP example of use☆32Updated 3 years ago
- CNN accelerator☆26Updated 7 years ago
- ☆8Updated last year
- ☆20Updated 5 years ago
- SoC Based on ARM Cortex-M3☆25Updated 6 months ago
- Development of a Network on Chip Simulation using SystemC.☆31Updated 7 years ago
- The memory model was leveraged from micron.☆19Updated 6 years ago
- DMA controller for CNN accelerator☆12Updated 7 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆24Updated 4 years ago
- Ratatoskr NoC Simulator☆21Updated 3 years ago
- HLS for Networks-on-Chip☆31Updated 3 years ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆12Updated 9 months ago
- ☆37Updated 5 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆31Updated last year
- ☆25Updated 4 years ago
- WISHBONE Interconnect☆11Updated 7 years ago