zhujingyang520 / vlsi_project
The template for VLSI project
☆17Updated 5 years ago
Alternatives and similar repositories for vlsi_project:
Users that are interested in vlsi_project are comparing it to the libraries listed below
- This is a project integrating HLS IP and CortexA9 on Zynq. This CPU-FPGA project, for a Matrix Multiplication Dataflow, is implemented wi…☆21Updated 5 years ago
- RTL code of some arbitration algorithm☆13Updated 5 years ago
- SRAM☆21Updated 4 years ago
- AXI3 Bus Functional Models (Initiator & Target)☆28Updated 2 years ago
- IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system☆19Updated last month
- ☆26Updated 5 years ago
- To design test bench of the APB protocol☆17Updated 4 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆48Updated 3 years ago
- verification of simple axi-based cache☆18Updated 5 years ago
- Binary Single Precision Floating-point Fused Multiply-Add Unit Design (Verilog HDL)☆18Updated 11 years ago
- Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms☆25Updated 3 years ago
- ☆31Updated 5 years ago
- The memory model was leveraged from micron.☆22Updated 7 years ago
- The Verilog source code for DRUM approximate multiplier.☆29Updated last year
- Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.☆18Updated 7 months ago
- General Purpose AXI Direct Memory Access☆48Updated 10 months ago
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆18Updated 7 years ago
- DUTH RISC-V Microprocessor☆19Updated 3 months ago
- CNN accelerator using NoC architecture☆16Updated 6 years ago
- A project on hardware design for convolutional neural network. This neural network is of 2 layers with 400 inputs in the first layer. Thi…☆18Updated 7 years ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆44Updated 3 years ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆14Updated last year
- ☆47Updated 2 years ago
- This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of raven_soc which was taped-out by Efables…☆30Updated 4 years ago
- CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations☆19Updated 7 years ago
- ☆19Updated 5 years ago
- CNN accelerator☆28Updated 7 years ago
- APB Logic☆17Updated 3 months ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆29Updated 8 years ago
- A systolic array matrix multiplier☆24Updated 5 years ago