asinghani / 18224-s23-tapeoutLinks
Build infrastructure for class-wide tapeout for 18-224/624 Intro to Open Source Chip Design, Spring 2023
☆17Updated last year
Alternatives and similar repositories for 18224-s23-tapeout
Users that are interested in 18224-s23-tapeout are comparing it to the libraries listed below
Sorting:
- Proposed RISC-V Composable Custom Extensions Specification☆71Updated 3 weeks ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆62Updated 5 months ago
- ☆24Updated 9 months ago
- RTL data structure☆51Updated 3 weeks ago
- ☆45Updated 2 years ago
- APB UVC ported to Verilator☆11Updated last year
- Complete tutorial code.☆21Updated last year
- Advanced Architecture Labs with CVA6☆65Updated last year
- The OpenPiton Platform☆16Updated 11 months ago
- ☆47Updated 3 months ago
- ☆68Updated this week
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆86Updated last week
- Summer School Week 1 & 2 repo☆11Updated 3 years ago
- Curriculum for a university course to teach chip design using open source EDA tools☆95Updated last year
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆122Updated this week
- Open source RTL simulation acceleration on commodity hardware☆28Updated 2 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆51Updated 9 months ago
- Synthesizable Floating point unit written using Verilog. Supports 32-bit (Single-Precision) Multiplication, Addition and Division and Squ…☆59Updated 11 months ago
- A tool for synthesizing Verilog programs☆95Updated last week
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆85Updated last year
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆45Updated 3 years ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆104Updated 2 months ago
- ☆32Updated 6 months ago
- Lectures for the Agile Hardware Design course in Jupyter Notebooks☆101Updated 2 months ago
- Self checking RISC-V directed tests☆110Updated last month
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆57Updated 3 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆67Updated 6 months ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆111Updated last week
- Library of open source Process Design Kits (PDKs)☆48Updated 3 weeks ago
- RISC-V Nox core☆66Updated 3 months ago