Alternatives and similar repositories for ic_flow_platform

Users that are interested in ic_flow_platform are comparing it to the libraries listed below

• WilsonChen003 / HDLGen
  HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded f…
  ☆105Updated last year
• veripool / verilog-perl
  Verilog parser, preprocessor, and related tools for the Verilog-Perl package
  ☆140Updated last year
• adki / gen_amba
  AMBA bus generator including AXI, AHB, and APB
  ☆107Updated 4 years ago
• xbwpc / EDA_FeatureColle
  A collection of license features from a varity of EDA vendors
  ☆76Updated 2 months ago
• adki / gen_amba_2021
  AMBA bus generator including AXI4, AXI3, AHB, and APB
  ☆223Updated 2 years ago
• hyf6661669 / Synopsys-Documents
  Some useful documents of Synopsys
  ☆88Updated 3 years ago
• hellovimo / uvm_testbench_gen
  Novel GUI Based UVM Testbench Template Builder
  ☆144Updated 4 years ago
• Practical-UVM-Step-By-Step / Practical-UVM-Step-By-Step
  This is the main repository for all the examples for the book Practical UVM
  ☆204Updated 4 years ago
• taichi-ishitani / tnoc
  Network on Chip Implementation written in SytemVerilog
  ☆191Updated 3 years ago
• freecores / dma_axi
  AXI DMA 32 / 64 bits
  ☆121Updated 11 years ago
• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆176Updated last month
• zhajio1988 / YASA
  Yet Another Simulation Architecture
  ☆76Updated 5 years ago
• mflowgen / mflowgen
  mflowgen -- A Modular ASIC/FPGA Flow Generator
  ☆268Updated this week
• tpoikela / uvm-python
  UVM 1.2 port to Python
  ☆253Updated 8 months ago
• andres-mancera / ethernet_10ge_mac_SV_UVM_tb
  SystemVerilog-based UVM testbench for an Ethernet 10GE MAC core
  ☆149Updated 7 years ago
• RV-BOSC / OpenNoC
  ☆198Updated 3 months ago
• kumarrishav14 / AXI
  VIP for AXI Protocol
  ☆155Updated 3 years ago
• courageheart / AMBA_APB_SRAM
  AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM an…
  ☆181Updated 7 years ago
• funningboy / uvm_axi
  uvm AXI BFM(bus functional model)
  ☆261Updated 12 years ago
• luuvish / amba3-vip
  amba3 apb/axi vip
  ☆51Updated 10 years ago
• GodelMachine / AHB2
  AMBA AHB 2.0 VIP in SystemVerilog UVM
  ☆155Updated 5 years ago
• marcoz001 / axi-uvm
  yet another AXI testbench repo. ;) This is for my UVM practice. https://marcoz001.github.io/axi-uvm/
  ☆128Updated 7 years ago
• Verdvana / AXI4_Interconnect
  AXI总线连接器
  ☆104Updated 5 years ago
• taichi-ishitani / tvip-axi
  AMBA AXI VIP
  ☆426Updated last year
• aignacio / ravenoc
  RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
  ☆179Updated 11 months ago
• mayurkubavat / UVM-Examples
  UVM examples and projects
  ☆146Updated 3 months ago
• The-OpenROAD-Project / asap7
  ☆201Updated 7 months ago
• gupta409 / Processor-UVM-Verification
  System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment
  ☆108Updated 9 months ago
• seabeam / yuu_ahb
  UVM AHB VIP
  ☆87Updated last month
• ananthbhat94 / DDR4MemoryController
  HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.
  ☆82Updated 7 years ago