Alternatives and similar repositories for ic_flow_platform

Users that are interested in ic_flow_platform are comparing it to the libraries listed below

• WilsonChen003 / HDLGen
  HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded f…
  ☆110Updated 2 years ago
• veripool / verilog-perl
  Verilog parser, preprocessor, and related tools for the Verilog-Perl package
  ☆145Updated 2 years ago
• hyf6661669 / Synopsys-Documents
  Some useful documents of Synopsys
  ☆96Updated 4 years ago
• mflowgen / mflowgen
  mflowgen -- A Modular ASIC/FPGA Flow Generator
  ☆280Updated 2 months ago
• hellovimo / uvm_testbench_gen
  Novel GUI Based UVM Testbench Template Builder
  ☆149Updated 4 years ago
• tpoikela / uvm-python
  UVM 1.2 port to Python
  ☆259Updated last year
• The-OpenROAD-Project / asap7
  ☆234Updated 10 months ago
• adki / gen_amba
  AMBA bus generator including AXI, AHB, and APB
  ☆119Updated 4 years ago
• Practical-UVM-Step-By-Step / Practical-UVM-Step-By-Step
  This is the main repository for all the examples for the book Practical UVM
  ☆216Updated 5 years ago
• adki / gen_amba_2021
  AMBA bus generator including AXI4, AXI3, AHB, and APB
  ☆238Updated 2 years ago
• freecores / dma_axi
  AXI DMA 32 / 64 bits
  ☆124Updated 11 years ago
• RV-BOSC / OpenNoC
  ☆220Updated 7 months ago
• mflowgen / freepdk-45nm
  ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen
  ☆201Updated 5 years ago
• zhajio1988 / YASA
  Yet Another Simulation Architecture
  ☆79Updated 5 years ago
• andres-mancera / ethernet_10ge_mac_SV_UVM_tb
  SystemVerilog-based UVM testbench for an Ethernet 10GE MAC core
  ☆160Updated 7 years ago
• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆208Updated 5 months ago
• xbwpc / EDA_FeatureColle
  A collection of license features from a varity of EDA vendors
  ☆85Updated 5 months ago
• brentwang-lab / uvm_tb_gen
  This is for uvm_tb_gen
  ☆51Updated 11 months ago
• taichi-ishitani / tnoc
  Network on Chip Implementation written in SytemVerilog
  ☆198Updated 3 years ago
• mayurkubavat / UVM-Examples
  UVM examples and projects
  ☆156Updated 7 months ago
• courageheart / AMBA_APB_SRAM
  AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM an…
  ☆191Updated 7 years ago
• Practical-UVM-Step-By-Step / Practical-UVM-IEEE-Edition
  This is the repository for the IEEE version of the book
  ☆78Updated 5 years ago
• accellera-official / uvm-core
  ☆114Updated last year
• cluelogic / uvm-tutorial-for-candy-lovers
  Source code repo for UVM Tutorial for Candy Lovers
  ☆204Updated 8 years ago
• GodelMachine / AHB2
  AMBA AHB 2.0 VIP in SystemVerilog UVM
  ☆160Updated 5 years ago
• luuvish / amba3-vip
  amba3 apb/axi vip
  ☆53Updated 10 years ago
• limerainne / Dockerize-EDA
  [WIP] Dockerize Synopsys/Cadence EDA tools
  ☆96Updated 6 years ago
• troyguo / awesome-dv
  Awesome ASIC design verification
  ☆341Updated 4 years ago
• zhajio1988 / Open_RegModel
  Use ORDT and systemRDL tools to generate C/Verilog header files, register RTL, UVM register models, and docs from compiled SystemRDL.
  ☆74Updated 6 years ago
• accellera / uvm
  ☆60Updated 9 years ago