Alternatives and similar repositories for ic_flow_platform

Users that are interested in ic_flow_platform are comparing it to the libraries listed below

• WilsonChen003 / HDLGen
  HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded f…
  ☆102Updated last year
• veripool / verilog-perl
  Verilog parser, preprocessor, and related tools for the Verilog-Perl package
  ☆137Updated last year
• hyf6661669 / Synopsys-Documents
  Some useful documents of Synopsys
  ☆76Updated 3 years ago
• hellovimo / uvm_testbench_gen
  Novel GUI Based UVM Testbench Template Builder
  ☆138Updated 4 years ago
• xbwpc / EDA_FeatureColle
  A collection of license features from a varity of EDA vendors
  ☆69Updated last year
• tpoikela / uvm-python
  UVM 1.2 port to Python
  ☆252Updated 5 months ago
• zhajio1988 / YASA
  Yet Another Simulation Architecture
  ☆74Updated 4 years ago
• adki / gen_amba_2021
  AMBA bus generator including AXI4, AXI3, AHB, and APB
  ☆209Updated 2 years ago
• andres-mancera / ethernet_10ge_mac_SV_UVM_tb
  SystemVerilog-based UVM testbench for an Ethernet 10GE MAC core
  ☆144Updated 7 years ago
• luuvish / amba3-vip
  amba3 apb/axi vip
  ☆50Updated 10 years ago
• Practical-UVM-Step-By-Step / Practical-UVM-Step-By-Step
  This is the main repository for all the examples for the book Practical UVM
  ☆199Updated 4 years ago
• funningboy / uvm_axi
  uvm AXI BFM(bus functional model)
  ☆250Updated 12 years ago
• RV-BOSC / OpenNoC
  ☆170Updated 3 weeks ago
• emwzq / example_uvm
  UVM实战随书源码
  ☆52Updated 6 years ago
• kumarrishav14 / AXI
  VIP for AXI Protocol
  ☆139Updated 3 years ago
• mflowgen / mflowgen
  mflowgen -- A Modular ASIC/FPGA Flow Generator
  ☆257Updated this week
• naragece / uvm-testbench-tutorial-simple-adder
  A basic testbench made for educational purposes using SystemVerilog and the Universal Verification Methodology
  ☆105Updated 11 years ago
• adki / gen_amba
  AMBA bus generator including AXI, AHB, and APB
  ☆105Updated 3 years ago
• cluelogic / uvm-tutorial-for-candy-lovers
  Source code repo for UVM Tutorial for Candy Lovers
  ☆192Updated 8 years ago
• freecores / dma_axi
  AXI DMA 32 / 64 bits
  ☆115Updated 11 years ago
• Practical-UVM-Step-By-Step / Practical-UVM-IEEE-Edition
  This is the repository for the IEEE version of the book
  ☆66Updated 4 years ago
• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆161Updated last month
• accellera / uvm
  ☆54Updated 9 years ago
• courageheart / AMBA_APB_SRAM
  AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM an…
  ☆173Updated 6 years ago
• GodelMachine / AHB2
  AMBA AHB 2.0 VIP in SystemVerilog UVM
  ☆151Updated 5 years ago
• marcoz001 / axi-uvm
  yet another AXI testbench repo. ;) This is for my UVM practice. https://marcoz001.github.io/axi-uvm/
  ☆121Updated 7 years ago
• accellera-official / uvm-core
  ☆87Updated 10 months ago
• troyguo / awesome-dv
  Awesome ASIC design verification
  ☆311Updated 3 years ago
• taichi-ishitani / tnoc
  Network on Chip Implementation written in SytemVerilog
  ☆185Updated 2 years ago
• cluelogic / cluelib
  A generic class library in SystemVerilog
  ☆84Updated 4 years ago