EECS150 / asic-labs-fa22
☆19Updated last year
Related projects ⓘ
Alternatives and complementary repositories for asic-labs-fa22
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆39Updated last year
- Open source process design kit for 28nm open process☆42Updated 6 months ago
- Open source ISS and logic RISC-V 32 bit project☆40Updated this week
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆57Updated 3 weeks ago
- A Fast, Low-Overhead On-chip Network☆134Updated 2 weeks ago
- This is a tutorial on standard digital design flow☆72Updated 3 years ago
- Introductory course into static timing analysis (STA).☆63Updated this week
- Advanced Architecture Labs with CVA6☆48Updated 9 months ago
- Proposed RISC-V Composable Custom Extensions Specification☆67Updated 6 months ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆47Updated 2 years ago
- A GPU acceleration flow for RTL simulation with batch stimulus☆92Updated 7 months ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆59Updated 3 years ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆58Updated last week
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆60Updated 7 months ago
- ☆73Updated last year
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆41Updated 2 weeks ago
- A configurable SRAM generator☆40Updated this week
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆75Updated this week
- EE 260 Winter 2017: Advanced VLSI Design☆58Updated 7 years ago
- General Purpose AXI Direct Memory Access☆44Updated 5 months ago
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆67Updated 10 months ago
- RISC-V Nox core☆61Updated 3 months ago
- ☆37Updated 5 years ago
- ☆97Updated 3 months ago
- Like VexRiscv, but, Harder, Better, Faster, Stronger☆103Updated this week
- fakeram generator for use by researchers who do not have access to commercial ram generators☆32Updated last year
- A simple DDR3 memory controller☆51Updated last year
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆140Updated last year
- A Style Guide for the Chisel Hardware Construction Language☆106Updated 3 years ago
- RISCV model for Verilator/FPGA targets☆44Updated 5 years ago