Alternatives and similar repositories for pystateye

Users that are interested in pystateye are comparing it to the libraries listed below

• tchancarusone / Wireline-ChModel-Matlab
  Repository of Matlab tools for analysis of wireline signal integrity and transceiver simulation
  ☆12Updated 5 years ago
• savob / statopt-python
  StatOpt Tool in Python
  ☆14Updated last year
• richard259 / serdespy
  Python library for SerDes modelling
  ☆73Updated last year
• kevjzheng / JLSD
  ☆24Updated last year
• capn-freako / PyAMI
  Python package for IBIS-AMI model development and testing
  ☆30Updated last week
• ChrisZonghaoLi / gm_id_gf180mcu
  This repo contains introduction of gm/id method and its application to some OTA design examples.
  ☆18Updated last year
• sgherbst / msdsl
  Automatic generation of real number models from analog circuits
  ☆45Updated last year
• arutema47 / sar-adc
  Model SAR ADC with python!
  ☆22Updated 3 years ago
• anlit75 / ADPLL
  All Digital Phase-Locked Loop (ADPLL)
  ☆20Updated last year
• capn-freako / ibisami
  A public domain IBIS-AMI model creation infrastructure for all to share.
  ☆16Updated 8 months ago
• fengqzHD / gmIdNeoKit
  Gm Id Kit with GUI to Work with Matlab Data file similar to Prof. Boris Murmann's gm/ID Starter Kit
  ☆48Updated 5 years ago
• ashwith / pyMOSChar
  Python port of Prof. Boris Murmann's gm/ID Starter Kit
  ☆54Updated 8 years ago
• gmagno / spyci
  A tiny Python package to parse spice raw data files.
  ☆53Updated 2 years ago
• capn-freako / PyBERT
  Serial communication link bit error rate tester simulator, written in Python.
  ☆114Updated last week
• johnkustin / bandgapReferenceCircuit
  repository for a bandgap voltage reference in SKY130 technology
  ☆41Updated 2 years ago
• sgherbst / svreal
  Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats
  ☆48Updated 4 years ago
• ucb-art / laygo
  LAYout with Gridded Objects
  ☆29Updated 5 years ago
• StanfordVLSI / dragonphy2
  Open Source PHY v2
  ☆31Updated last year
• capn-freako / PyChOpMarg
  Python implementation of COM, as per IEEE 802.3-22 Annex 93A.
  ☆15Updated 3 months ago
• NeuroFan / Algorithmic-SAR-ADC-simulation-files
  HSPICE and MATLAB simulation files of a tracking SAR ADC
  ☆26Updated last year
• muhammadaldacher / Analog-design-of-10-GbaseKR-high-speed-serial-link-transceiver-in-65-nm-CMOS
  This project presents a 10Gb/s transceiver design using 65nm CMOS process, based on a 10GBASE-KR standard.
  ☆24Updated 6 years ago
• ucb-art / bag
  BAG framework
  ☆30Updated 10 months ago
• das-dias / novaad
  An EDA tool for automatic device sizing using Gm/Id method.
  ☆14Updated last year
• ucb-art / BAG2_cds_ff_mpt
  BAG2 workspace for fake PDK (cds_ff_mpt)
  ☆59Updated 5 years ago
• phonon / sar-adc-metastability
  Code for "Understanding Metastability in SAR ADCs: Part II: Asynchronous"
  ☆11Updated 3 years ago
• mabrains / Analog_blocks
  Design of Analog Blocks in Skywaters 130nm meeting corners: different flavors of OTA, BandGap, LDO.
  ☆28Updated 3 years ago
• bmurmann / Ngspice-on-Colab
  Sandbox for experimenting with Ngspice and open PDKs in Google Colab
  ☆25Updated last year
• KenKundert / psf_utils
  Read Spectre PSF files
  ☆69Updated 3 months ago
• niftylab / laygo2
  LAYout with Gridded Objects v2
  ☆65Updated 4 months ago
• Vlsir / Vlsir
  Interchange formats for chip design.
  ☆33Updated 5 months ago