XAli-SHX / FPGA-Implementation-of-Image-Processing-for-MNIST-Dataset-Based-on-CNN-AlgorithmView on GitHub
FPGA Implementation of Image Processing for MNIST Dataset Based on Convolutional Neural Network Algorithm (CNN)
☆11Dec 12, 2023Updated 2 years ago
Alternatives and similar repositories for FPGA-Implementation-of-Image-Processing-for-MNIST-Dataset-Based-on-CNN-Algorithm
Users that are interested in FPGA-Implementation-of-Image-Processing-for-MNIST-Dataset-Based-on-CNN-Algorithm are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- 本项目使用 Vivado 和 SDK 工程软件上完成系统设计和生成相关部署文件,并在 ARM+FPGA 完成项目部署,实现通过摄取图片并通过 ARM+FPGA 综合部署和加速识别算法,并通过显示驱动,在显示屏上显示摄像头原图和识别结果。☆10Aug 12, 2022Updated 4 years ago
- ☆15Nov 22, 2022Updated 3 years ago
- A Verilog implementation of a hand-written digit recognition Neural Network☆11Nov 16, 2024Updated last year
- This repository contains the design and implementation of a Spiking Neural Network (SNN) Processor. Spiking Neural Networks are a biologi…☆12Oct 19, 2024Updated 2 years ago
- A CNN-based hardware digit/image recognition module designed on PyTorch and then implemented with Verilog on FPGA☆22Oct 17, 2022Updated 4 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- EE 272B - VLSI Design Project☆15Jun 24, 2021Updated 5 years ago
- High Performance Network Laboratory WebPage☆27Sep 22, 2026Updated last month
- ☆12Dec 18, 2022Updated 3 years ago
- TinySNN lets you build tiny spiking neural networks in C.☆10Oct 13, 2020Updated 6 years ago
- Initial toolchain for FeNN FPGA SNN accelerator☆18Updated this week
- CNN Accelerator in Frequency Domain☆12Feb 22, 2020Updated 6 years ago
- Project in course “FPGA Design for Communication Systems”☆16Dec 30, 2023Updated 2 years ago
- Arrhythmia Detection Using Algorithm and Hardware Co-design for Neural Network Inference Accelerators☆16Jun 5, 2023Updated 3 years ago
- Track line editing history in VSCode☆13Feb 7, 2026Updated 8 months ago
- Open source password manager - Proton Pass • AdSecurely store, share, and autofill your credentials with Proton Pass, the end-to-end encrypted password manager trusted by millions.
- A DotLoadersPack-Android fork with additional features and fixes☆12May 3, 2023Updated 3 years ago
- 双目图像拼接,双目相机立体匹配,得到深度图像等。☆11Apr 27, 2020Updated 6 years ago
- ☆29Feb 5, 2020Updated 6 years ago
- MIPS Processor, BNN Accelerator, AXI4 interface, Cache Controller and LRU replacement☆16Nov 4, 2022Updated 3 years ago
- ov5640_sdram_vga_FPGA☆10Mar 27, 2023Updated 3 years ago
- verilog CNN generator for FPGA☆34Jan 4, 2021Updated 5 years ago
- ☆11Jul 26, 2017Updated 9 years ago
- fpga跑sobel识别算法☆49Mar 15, 2021Updated 5 years ago
- CPU implementation of the Image stitching using FAST. For FPGA implementation visit tharaka27-SocStitcher.☆12Jun 19, 2020Updated 6 years ago
- End-to-end encrypted cloud storage - Proton Drive • AdSpecial offer: 40% Off Yearly / 80% Off First Month. Protect your most important files, photos, and documents from prying eyes.
- EO-CNN: An Enhanced CNN Model Trained by Equilibrium Optimization for Traffic Transportation Prediction☆14Jun 6, 2020Updated 6 years ago
- Radio Spectrum Viewer and Software Defined Radio in a cheap FPGA board☆21Apr 24, 2023Updated 3 years ago
- An FPGA design for simulating biological neurons☆19Jul 5, 2024Updated 2 years ago
- 基于C++&OPENCV 的全景图像拼接☆11Mar 21, 2019Updated 7 years ago
- ☆11Mar 22, 2022Updated 4 years ago
- ☆11Oct 26, 2023Updated 3 years ago
- ☆13Apr 9, 2018Updated 8 years ago
- Implementation of the BitLinear layer from: The Era of 1-bit LLMs: All Large Language Models are in 1.58 Bits☆13Sep 11, 2024Updated 2 years ago
- Systolic matrix multiplication kernel implemented on Xilinx PYNQ FPGA board☆18Jun 23, 2020Updated 6 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Converting Boolean expressions to CMOS Circuits☆11Oct 6, 2020Updated 6 years ago
- Implementation of the core Transformer architecture in pure C☆15Sep 8, 2024Updated 2 years ago
- Loss-aware automatic selection of structured pruning criteria for deep neural network acceleration. ✅ Published in Image and Vision Compu…☆12Aug 30, 2024Updated 2 years ago
- Integration of SIFT and LES Algorithms☆14May 6, 2024Updated 2 years ago
- yolov5-acceleration-fpga☆11Jun 25, 2025Updated last year
- A neural network built in Verilog for the DE1-SoC FPGA board for handwritten digit recognition.☆19Oct 11, 2019Updated 7 years ago
- Framework for radix encoded SNN on FPGA☆18Dec 7, 2021Updated 4 years ago