An accurate Electro Cardio Graph system, with peak detection and counting mechanism programmed in Verilog.
☆14Jan 6, 2019Updated 7 years ago
Alternatives and similar repositories for ECG-Verilog-FPGA
Users that are interested in ECG-Verilog-FPGA are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Arrhythmia Detection Using Algorithm and Hardware Co-design for Neural Network Inference Accelerators☆16Jun 5, 2023Updated 2 years ago
- Verilog HDL implementation of an ECHO machine and an FIR filter that filters out a specific noise. More details provided in individual fi…☆10Aug 25, 2019Updated 6 years ago
- ☆13Dec 30, 2020Updated 5 years ago
- ECG signals acquired using a sensor has a lot of noise due to lung sounds and EMG. The noise due to lung sounds, EMG can be removed by us…☆13Nov 8, 2019Updated 6 years ago
- AXI4-Stream FIR filter IP☆19Nov 4, 2022Updated 3 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting with the flexibility to host WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Cloudways by DigitalOcean.
- ☆25May 9, 2023Updated 2 years ago
- 郑州大学疫情自动打卡☆10Sep 16, 2023Updated 2 years ago
- A custom coprocessor and SoC for hardware security experiments in electronics.☆12May 20, 2017Updated 8 years ago
- Analysing arterial pulse waves☆18May 25, 2021Updated 4 years ago
- KENN: Knowledge Enhanced Neural Networks☆12Sep 11, 2020Updated 5 years ago
- FIR,FFT based on Verilog☆14Dec 3, 2017Updated 8 years ago
- Optimize hyperparameters for a support vector machine classifier (SVC) in scikit-learn via genetic algorithm☆14Apr 20, 2018Updated 7 years ago
- DDS (Direct Digital Synthesis) Analog Devices AD9910 Arduino Shield by GRA & AFCH☆12Apr 11, 2025Updated 11 months ago
- Haar wavelet based Discrete wavelet transform for ECG feature extraction in Verilog☆20Jul 21, 2015Updated 10 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- ☆14Oct 24, 2022Updated 3 years ago
- 第四届全国大学生嵌入式比赛SoC☆11Apr 1, 2022Updated 3 years ago
- FIR band-pass filter using Verilog HDL.☆13Sep 6, 2020Updated 5 years ago
- The PE for the second generation CGRA (garnet).☆18Feb 22, 2026Updated last month
- ☆19Oct 7, 2025Updated 5 months ago
- A design of 15-order FIR filter using Verilog, with modulation and demodulation system using MATLAB☆10Aug 15, 2020Updated 5 years ago
- Documentation for the entire CGRAFlow☆19Sep 17, 2021Updated 4 years ago
- ☆17Jan 11, 2021Updated 5 years ago
- Digital Design Lab Spring 2019 Final Project☆13Jun 17, 2019Updated 6 years ago
- Wordpress hosting with auto-scaling on Cloudways • AdFully Managed hosting built for WordPress-powered businesses that need reliable, auto-scalable hosting. Cloudways SafeUpdates now available.
- Implemented Machine Learning and Artificial Intelligence model to detect the different disease on plants using the images.☆31Apr 10, 2024Updated last year
- Implementation of the CMAC keyed hash function using AES as block cipher.☆16Apr 2, 2025Updated 11 months ago
- A 66-order (67 taps) hamming FIR LPF Filter is to be designed with a cutoff frequency of 200 KHZ for a sampling frequency of 1 MHZ☆14Feb 17, 2023Updated 3 years ago
- AES☆15Oct 4, 2022Updated 3 years ago
- Zedboard projects☆11May 15, 2016Updated 9 years ago
- AES-128 Encryption☆10Jul 17, 2014Updated 11 years ago
- Raw image file reader, written in Java, as part of an ongoing personal study project.☆17Aug 1, 2019Updated 6 years ago
- A repository for exploring LLM-assisted code conversion to TL-Verilog.☆14Feb 20, 2026Updated last month
- Word stress library☆12Aug 15, 2024Updated last year
- DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations☆21May 4, 2017Updated 8 years ago
- Design a median filter for a Generic RGB image.☆14Mar 6, 2019Updated 7 years ago
- IEEE Executive project for the year 2021-2022☆11Nov 22, 2022Updated 3 years ago
- Express DLA implementation for FPGA, revised based on NVDLA.☆11Oct 17, 2019Updated 6 years ago
- ☆13Mar 3, 2022Updated 4 years ago
- A Bayesian spatio-temporal interaction model for epidemiology.☆25Oct 28, 2019Updated 6 years ago
- LSTM neural network (verilog)☆15Dec 5, 2018Updated 7 years ago