CountingLogic / ECG-Verilog-FPGALinks
An accurate Electro Cardio Graph system, with peak detection and counting mechanism programmed in Verilog.
☆14Updated 6 years ago
Alternatives and similar repositories for ECG-Verilog-FPGA
Users that are interested in ECG-Verilog-FPGA are comparing it to the libraries listed below
Sorting:
- Convolutional Neural Network Implemented in Verilog for System on Chip☆28Updated 6 years ago
- ☆37Updated 6 years ago
- AHB DMA 32 / 64 bits☆56Updated 11 years ago
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆31Updated 4 years ago
- tpu-systolic-array-weight-stationary☆24Updated 4 years ago
- Some attempts to build CNN on PYNQ.☆25Updated 6 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆82Updated 2 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆68Updated last year
- MIPS Processor, BNN Accelerator, AXI4 interface, Cache Controller and LRU replacement☆13Updated 3 years ago
- This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.☆53Updated 8 years ago
- A verilog implementation for Network-on-Chip☆77Updated 7 years ago
- Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…☆22Updated 4 years ago
- AXI Interconnect☆54Updated 4 years ago
- FFT implementation using CORDIC algorithm written in Verilog.☆33Updated 7 years ago
- 3×3脉动阵列乘法器☆48Updated 6 years ago
- A project on hardware design for convolutional neural network. This neural network is of 2 layers with 400 inputs in the first layer. Thi…☆18Updated 7 years ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆37Updated 3 years ago
- ☆26Updated 4 years ago
- syn script for DC Compiler☆14Updated 3 years ago
- ☆62Updated last year
- SystemVerilog files for lab project on a DNN hardware accelerator☆18Updated 4 years ago
- This repository contains all the parameters you need to synthesize the AlexNet by using Vivado High Level Synthesis.☆21Updated 7 years ago
- A Verilog design of LeNet-5, a Convolutional Neural Network architecture☆34Updated 5 years ago
- AXI4 BFM in Verilog☆34Updated 8 years ago
- Example of a full DC synthesis script for a simple design☆12Updated 6 years ago
- ☆19Updated 6 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆42Updated 3 years ago
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆36Updated 2 years ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆48Updated last year
- Convolution Neural Network of vgg19 model in verilog☆49Updated 7 years ago