ShichenQiao / ECE554_SP23_FPGA_Handwriting_RecognitionLinks
Senior Design Project at UW-Madison ECE
☆15Updated 2 years ago
Alternatives and similar repositories for ECE554_SP23_FPGA_Handwriting_Recognition
Users that are interested in ECE554_SP23_FPGA_Handwriting_Recognition are comparing it to the libraries listed below
Sorting:
- Project is about designing a Trained Neural Network on FPGA to classify an Image Input using CNN.☆157Updated 4 years ago
- Convolutional Neural Network RTL-level Design☆70Updated 3 years ago
- This repository hosts the code for an FPGA based accelerator for convolutional neural networks☆161Updated last year
- A Verilog design of LeNet-5, a Convolutional Neural Network architecture☆35Updated 5 years ago
- This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Netw…☆187Updated last year
- Implementation of CNN using Verilog☆223Updated 7 years ago
- Convolutional accelerator kernel, target ASIC & FPGA☆226Updated 2 years ago
- 2023集创赛国二。基于脉动阵列写的一个简单的卷积层加速器,支持yolov3-tiny的第一层卷积层计算,可根据FPGA端DSP资源灵活调整脉动阵列的结构以实现不同的计算效率。☆197Updated 10 months ago
- Real time face detection based on Arm Cortex-M3 DesignStart and FPGA☆206Updated 2 years ago
- ☆283Updated last year
- A hardware implementation of CNN, written by Verilog and synthesized on FPGA☆239Updated 6 years ago
- FPGA实现动态图像识别☆22Updated 5 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆67Updated last year
- This project aims to design an 32-point FFT (Fast Fourier Transform) based DIT (decimation in time) Butterfly Algorithm with multiple clo…☆57Updated 2 years ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆27Updated 6 years ago
- 数字IC秋招项目、手撕代码☆38Updated last year
- FPGA/AES/LeNet/VGG16☆108Updated 7 years ago
- MNIST using tensorflow, c++ and fpga (zynq7010)☆25Updated 2 years ago
- ☆69Updated 9 years ago
- A 16-bit by 16-bit signed binary multiplier based on the Radix-4 Booth algorithm and Wallace Tree reduction☆57Updated last year
- achieve softmax in PYNQ with heterogeneous computing.☆65Updated 6 years ago
- Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…☆22Updated 4 years ago
- AXI总线连接器☆104Updated 5 years ago
- An LeNet RTL implement onto FPGA☆49Updated 7 years ago
- The Canny Edge Detection algorithm is implemented on an FPGA using only Verilog code and no Intellectual Property, making it convenient t…☆44Updated last year
- fpga跑sobel识别算法☆39Updated 4 years ago
- IC Verification & SV Demo☆54Updated 3 years ago
- 清華大學 | 積體電路設計實 驗 (IC LAB) | 110上☆45Updated 2 years ago
- 网络训练、图像预处理以及部分hend功能是基于pc端实现的,只有主干网络部署在fpga上,片上资源无法支持整个网络所需资源,建议添加外部存储及DDR☆123Updated 2 years ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆47Updated last year