ShichenQiao / ECE554_SP23_FPGA_Handwriting_RecognitionLinks
Senior Design Project at UW-Madison ECE
☆15Updated 2 years ago
Alternatives and similar repositories for ECE554_SP23_FPGA_Handwriting_Recognition
Users that are interested in ECE554_SP23_FPGA_Handwriting_Recognition are comparing it to the libraries listed below
Sorting:
- FPGA实现动态图像识别☆21Updated 4 years ago
- Convolutional Neural Network RTL-level Design☆55Updated 3 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆64Updated 9 months ago
- This project aims to design an 32-point FFT (Fast Fourier Transform) based DIT (decimation in time) Butterfly Algorithm with multiple clo…☆54Updated last year
- Step by step tutorial for building CortexM0 SoC☆38Updated 3 years ago
- Pipeline FFT Implementation in Verilog HDL☆117Updated 6 years ago
- 2023集创赛国二。基于脉动阵列写的一个简单的卷积层加速器,支持yolov3-tiny的第一层卷积层计算,可根据FPGA端DSP资源灵活调整脉动阵列的结构以实现不同的计算效率。☆178Updated 7 months ago
- A Verilog design of LeNet-5, a Convolutional Neural Network architecture☆33Updated 4 years ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆27Updated 6 years ago
- 2022年全国大学生嵌入式芯片与系统设计竞赛——FPGA创新设计竞赛紫光同创赛道视频色度亮度提取赛题设计源文件☆32Updated 2 years ago
- Project is about designing a Trained Neural Network on FPGA to classify an Image Input using CNN.☆148Updated 4 years ago
- 数字IC秋招项目、手撕代码☆35Updated last year
- ☆55Updated 11 months ago
- upgrade to e203 (a risc-v core)☆44Updated 4 years ago
- fpga跑sobel识别算法☆35Updated 4 years ago
- ☆38Updated last week
- Some attempts to build CNN on PYNQ.☆24Updated 5 years ago
- The Canny Edge Detection algorithm is implemented on an FPGA using only Verilog code and no Intellectual Property, making it convenient t…☆38Updated last year
- 使用FPGA实现CNN模型☆15Updated 5 years ago
- ☆19Updated 5 years ago
- 2018第二届全国大学生FPGA创新设计邀请赛的作品☆59Updated 6 years ago
- AXI总线连接器☆97Updated 5 years ago
- Use Verilog to complete the design of various digital circuits, including common interfaces, such as UART, Bluetooth, IIC, AMBA, etc. It …☆27Updated 4 years ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆31Updated 2 years ago
- FFT implement by verilog_测试验证已通过☆57Updated 8 years ago
- A final semester based group project for EE4218: Embedded Hardware System Design module in NUS where I worked with my teammate to perform…☆15Updated 2 years ago
- MNIST using tensorflow, c++ and fpga (zynq7010)☆25Updated 2 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆75Updated last year
- 3 layern artificial ANN to recognize handwritten digits and implement in FPGA☆8Updated 4 years ago
- SPI interface connect to APB BUS with Verilog HDL☆32Updated 3 years ago