cascode-labs / virtueLinks
A Python and SKILL Framework for Cadence Virtuoso
☆49Updated last month
Alternatives and similar repositories for virtue
Users that are interested in virtue are comparing it to the libraries listed below
Sorting:
- Read Spectre PSF files☆72Updated last month
- Cadence SKILL utilities that have boosted my productivity considerably for 10+ years.☆53Updated last month
- Python port of Prof. Boris Murmann's gm/ID Starter Kit☆55Updated 8 years ago
- Parametric layout generator for digital, analog and mixed-signal integrated circuits☆70Updated this week
- Python script for generating lookup tables for the gm/ID design methodology and much more ...☆113Updated 2 months ago
- A seamless python to Cadence Virtuoso Skill interface☆252Updated 11 months ago
- Python interface for Cadence Spectre☆21Updated 6 months ago
- Inter Process Communication (IPC) between Python and Cadence Virtuoso☆83Updated 9 years ago
- Cadence Virtuoso Design Management System☆36Updated 3 years ago
- my cadence/virtuoso/icfb skill functions develloped over the years☆146Updated 3 weeks ago
- A python3 gm/ID starter kit☆62Updated 2 weeks ago
- Gm Id Kit with GUI to Work with Matlab Data file similar to Prof. Boris Murmann's gm/ID Starter Kit☆48Updated 5 years ago
- A tiny Python package to parse spice raw data files.☆53Updated 3 years ago
- Advanced integrated circuits 2023☆32Updated last year
- This project shows the design of a frequency synthesizer PLL system that produces a 1.92 GHz signal with a reference input of 30 MHz, wit…☆81Updated 2 years ago
- BAG framework☆31Updated last year
- This repo contains introduction of gm/id method and its application to some OTA design examples.☆18Updated 2 years ago
- Ancillary Material for the book "Systematic Design of Analog CMOS Circuits"☆177Updated 4 months ago
- repository for a bandgap voltage reference in SKY130 technology☆41Updated 3 years ago
- Code for "Understanding Metastability in SAR ADCs: Part II: Asynchronous"☆11Updated 3 years ago
- MATLAB toolbox for interfacing with the Cadence Virtuoso IC Design System☆30Updated 8 years ago
- GDSII File Parsing, IC Layout Analysis, and Parameter Extraction☆129Updated 2 years ago
- This project shows how to design a clock bootstrapped circuit to improve the nonlinearity of the switch used in Track & Hold circuit. A c…☆12Updated 6 years ago
- Connect Cadence Virtuoso to a Python client using sockets.☆18Updated 5 years ago
- A simple MOSFET model with only 5-DC-parameters for circuit simulation☆50Updated 5 months ago
- Cadence Virtuoso Git Integration written in SKILL++☆158Updated 3 years ago
- Python library for SerDes modelling☆82Updated last year
- Sandbox for experimenting with Ngspice and open PDKs in Google Colab☆28Updated last year
- This project is about designing a 1.5 bit stage Pipeline ADC & the OpAmp required for its MDAC.☆39Updated 3 years ago
- JKU IIC OSIC-Multitool for open-source IC (OSIC) design for SKY130.☆77Updated 10 months ago