Hardware Design Tool - Mixed Signal Simulation with Verilog
☆93Dec 18, 2024Updated last year
Alternatives and similar repositories for mixedsim
Users that are interested in mixedsim are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- skywater 130nm pdk☆52Jun 3, 2026Updated last week
- Parasitic capacitance analysis of foundry metal stackups☆18Jan 12, 2026Updated 4 months ago
- Fully-differential asynchronous non-binary 12-bit SAR-ADC in SKY130, free to re-use under Apache-2.0 license☆59Mar 13, 2025Updated last year
- ☆38Nov 14, 2024Updated last year
- The Xyce™ Parallel Electronic Simulator☆147Jun 1, 2026Updated last week
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- Characterizer☆37May 26, 2026Updated 2 weeks ago
- Integrated Circuit Layout☆62Feb 25, 2025Updated last year
- ☆39Apr 10, 2023Updated 3 years ago
- A tiny Python package to parse spice raw data files.☆53Dec 26, 2022Updated 3 years ago
- CVC: Circuit Validity Checker. Check for errors in CDL netlist.☆37Apr 9, 2026Updated 2 months ago
- A set of rules and recommendations for analog and digital circuit designers.☆31Nov 4, 2024Updated last year
- Python bindings for ngspice simulation engine☆73Mar 11, 2020Updated 6 years ago
- Skywater 130nm Klayout Device Generators PDK☆30Jul 12, 2024Updated last year
- Parasitic Extraction for KLayout☆44May 1, 2026Updated last month
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- BAG framework☆44Jul 24, 2024Updated last year
- Circuit Automatic Characterization Engine☆55Feb 7, 2025Updated last year
- Open-source repository for a standard-cell library characterizer using complete open-source tools☆62Updated this week
- Python port of Prof. Boris Murmann's gm/ID Starter Kit☆57Jun 30, 2017Updated 8 years ago
- XicTools: Xic graphical editor, WRspice circuit simulator, and accessories. for electronic design.☆182Jun 2, 2026Updated last week
- A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy an…☆469Jun 1, 2026Updated last week
- Primitives for GF180MCU provided by GlobalFoundries.☆13Jul 6, 2025Updated 11 months ago
- ☆21Nov 22, 2021Updated 4 years ago
- Version manager (and builder) for the Google sky130 and gf180mcu open-source PDKs☆79Nov 19, 2025Updated 6 months ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Gate-level visualization generator for SKY130-based chip designs.☆20Jul 22, 2021Updated 4 years ago
- A VHDL frontend for Yosys☆104Feb 27, 2017Updated 9 years ago
- Donald Amundson's Python interface to OpenAccess IC design data API☆18Apr 23, 2010Updated 16 years ago
- tools regarding on analog modeling, validation, and generation☆23Apr 11, 2023Updated 3 years ago
- Hardware Description Library☆93Feb 17, 2026Updated 3 months ago
- Examples and design pattern for VHDL verification☆15Apr 10, 2016Updated 10 years ago
- An open source generator for standard cell based memories.☆14Sep 6, 2016Updated 9 years ago
- WISHBONE Builder☆15Sep 10, 2016Updated 9 years ago
- COCOA: Collaborative Compendium on Analog Integrated Circuits☆28Jan 14, 2026Updated 4 months ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- This is the XDM netlist converter, used to convert PSPICE and HSPICE netists into Xyce format.☆25Feb 15, 2024Updated 2 years ago
- submission repository for efabless mpw6 shuttle☆31Jan 10, 2024Updated 2 years ago
- An OASIS and GDS2 (chip layout format) binary dump tool for debugging☆46Dec 5, 2017Updated 8 years ago
- 12 bit SAR ADC IP in Skywater 130 nm PDK☆30May 30, 2024Updated 2 years ago
- SpiceBind – spice inside HDL simulator☆58Jun 30, 2025Updated 11 months ago
- FOSS-ASIC-TOOLS is all in one container for SKY130 based design both Analog and Digital. Below is a list of the current tools already ins…☆108Aug 21, 2024Updated last year
- ☆57Sep 30, 2023Updated 2 years ago