Isotel / mixedsim
Hardware Design Tool - Mixed Signal Simulation with Verilog
☆76Updated 3 months ago
Alternatives and similar repositories for mixedsim:
Users that are interested in mixedsim are comparing it to the libraries listed below
- A current mode buck converter on the SKY130 PDK☆27Updated 3 years ago
- This repository is for (pre-)release versions of the Revolution EDA.☆42Updated 3 weeks ago
- Open-source RHBD (Radiation Hardened by Design) Standard-Cell Library for SKY130☆4Updated 4 months ago
- Open-source version of SLiCAP, implemented in python☆35Updated 3 months ago
- an inverter drawn in magic with makefile to simulate☆26Updated 2 years ago
- An Amateur Radio Transceiver IC (2.4 / 5 / 10 GHz)☆72Updated 3 years ago
- assorted library of utility cores for amaranth HDL☆86Updated 6 months ago
- Python script to transform a VCD file to wavedrom format☆75Updated 2 years ago
- XSCHEM symbol libraries for the Google-Skywater 130nm process design kit.☆60Updated this week
- Open source designs developed with IHP 130nm BiCMOS Open Source PDK. Documentation at https://ihp-open-ip.readthedocs.io/en/latest/☆36Updated last week
- An example of analogue design using open source IC design tools☆29Updated 3 years ago
- submission repository for efabless mpw6 shuttle☆30Updated last year
- An abstract language model of VHDL written in Python.☆51Updated last week
- A tube guitar amplifier power supply VHDL project☆16Updated 4 months ago
- ☆77Updated last year
- Conda recipes for FPGA EDA tools for simulation, synthesis, place and route and bitstream generation.☆100Updated last month
- ☆39Updated 2 years ago
- A padring generator for ASICs☆25Updated last year
- Small footprint and configurable JESD204B core☆41Updated 2 months ago
- A simple MOSFET model with only 5-DC-parameters for circuit simulation☆42Updated 8 months ago
- A Dockerfile with a collections of ready to use open source EDA tools: Yosys, SimbiYosys (with Z3, boolector and Yices2), nextpnr-ice40, …☆43Updated last year
- BAG framework☆40Updated 7 months ago
- Web-based HDL diagramming tool☆79Updated last year
- ☆46Updated last month
- ADMS is a code generator for the Verilog-AMS language☆98Updated 2 years ago
- A usable language reference for VHDL that is concise, direct, and easy to understand.☆25Updated last year
- LunaPnR is a place and router for integrated circuits☆46Updated 4 months ago
- 8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x mu…☆110Updated 3 years ago
- FuseSoC standard core library☆128Updated last month