Alternatives and similar repositories for mixedsim

Users that are interested in mixedsim are comparing it to the libraries listed below

• Qucs / ADMS
  ADMS is a code generator for some of Verilog-A
  ☆99Updated 2 years ago
• TinyTapeout / xschem-viewer
  Online viewer of Xschem schematic files
  ☆27Updated 8 months ago
• eskiyerli / revedaRelease
  This repository is for (pre-)release versions of the Revolution EDA.
  ☆42Updated this week
• wulffern / ciccreator
  Custom IC Creator (ciccreator) is a compiler that takes in a object definition file (JSON), a SPICE file, and a design rule file and outp…
  ☆34Updated 2 months ago
• yrrapt / amsat_txrx_ic
  An Amateur Radio Transceiver IC (2.4 / 5 / 10 GHz)
  ☆71Updated 3 years ago
• IHP-GmbH / IHP-Open-DesignLib
  Open source designs developed with IHP 130nm BiCMOS Open Source PDK. Documentation at https://ihp-open-ip.readthedocs.io/en/latest/
  ☆57Updated this week
• yrrapt / analogue_design_example
  An example of analogue design using open source IC design tools
  ☆29Updated 4 years ago
• mattvenn / magic-inverter
  an inverter drawn in magic with makefile to simulate
  ☆26Updated 3 years ago
• ACMmodel / MOSFET_model
  A simple MOSFET model with only 5-DC-parameters for circuit simulation
  ☆48Updated last month
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆78Updated 3 years ago
• westonb / open-pmic
  A current mode buck converter on the SKY130 PDK
  ☆29Updated 4 years ago
• hdl / containers
  Building and deploying container images for open source electronic design automation (EDA)
  ☆115Updated 10 months ago
• Paebbels / pyVHDLParser
  Streaming based VHDL parser.
  ☆84Updated last year
• lakshmi-sathi / avsdpll_1v8
  8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x mu…
  ☆114Updated 4 years ago
• wavedrom / zoom
  🔍 Zoomable Waveform viewer for the Web
  ☆44Updated 4 years ago
• gmagno / spyci
  A tiny Python package to parse spice raw data files.
  ☆53Updated 2 years ago
• amaranth-farm / amlib
  assorted library of utility cores for amaranth HDL
  ☆96Updated 11 months ago
• mbalestrini / gdsiistl
  Converts GDSII files to STL files.
  ☆37Updated last year
• ghdl / docker
  Scripts to build and use docker images including GHDL
  ☆41Updated 9 months ago
• VHDL / awesome-vhdl
  A curated list of awesome VHDL IP cores, frameworks, libraries, software and resources.
  ☆81Updated 5 years ago
• iic-jku / Circuit-Designers-Etiquette
  A set of rules and recommendations for analog and digital circuit designers.
  ☆29Updated 9 months ago
• Nic30 / d3-wave
  D3.js based wave (signal) visualizer
  ☆63Updated last week
• christoph-weiser / mpw6
  submission repository for efabless mpw6 shuttle
  ☆30Updated last year
• efabless / cace
  Circuit Automatic Characterization Engine
  ☆50Updated 6 months ago
• bluecheetah / bag
  BAG framework
  ☆41Updated last year
• YosysHQ / padring
  A padring generator for ASICs
  ☆25Updated 2 years ago
• tclarke / sky130radio
  components and examples for creating radio ICs using the open skywater 130nm PDK
  ☆19Updated 4 years ago
• capn-freako / PyBERT
  Serial communication link bit error rate tester simulator, written in Python.
  ☆111Updated 3 weeks ago
• efabless / caravel_user_project_analog
  ☆49Updated 6 months ago
• hdl4fpga / hdl4fpga
  VHDL library 4 FPGAs
  ☆181Updated this week