ucb-art / BAG_frameworkLinks
☆149Updated 2 years ago
Alternatives and similar repositories for BAG_framework
Users that are interested in BAG_framework are comparing it to the libraries listed below
Sorting:
- BAG2 workspace for fake PDK (cds_ff_mpt)☆57Updated 5 years ago
- ☆303Updated 3 months ago
- Machine Generated Analog IC Layout☆238Updated last year
- ☆150Updated 3 years ago
- ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen☆178Updated 5 years ago
- ☆169Updated 3 months ago
- mflowgen -- A Modular ASIC/FPGA Flow Generator☆257Updated 4 months ago
- LAYout with Gridded Objects v2☆57Updated this week
- Parser for LEF library files☆37Updated 4 years ago
- BAG framework☆29Updated 5 months ago
- PDK installer for open-source EDA tools and toolchains. Distributed with setups for the SkyWater 130nm and Global Foundries 180nm open p…☆335Updated last week
- ADC Performance Survey (ISSCC & VLSI Circuit Symposium)☆196Updated 2 weeks ago
- A seamless python to Cadence Virtuoso Skill interface☆216Updated 4 months ago
- Read Spectre PSF files☆64Updated 3 weeks ago
- AIB Generator: Analog hardware compiler for AIB PHY☆34Updated 4 years ago
- Standard Cell Library based Memory Compiler using FF/Latch cells☆147Updated last year
- ☆105Updated 5 years ago
- ☆44Updated last year
- Library for VLSI CAD Design Useful parsers and solvers' api are implemented.☆170Updated last month
- Fully Open Source FASOC generators built on top of open-source EDA tools☆282Updated last week
- ☆71Updated this week
- Tatum: A Fast, Flexible Static Timing Analysis (STA) Engine for Digital Circuits☆62Updated last year
- UCSD Detailed Router☆88Updated 4 years ago
- IEEE Solid-State Circuits Society (SSCS) Open-Source Ecosystem (OSE)☆184Updated last month
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆282Updated last month
- A complete open-source design-for-testing (DFT) Solution☆159Updated 3 weeks ago
- This is a tutorial on standard digital design flow☆78Updated 4 years ago
- A Standalone Structural Verilog Parser☆92Updated 3 years ago
- Verilog-A simulation models☆74Updated last week
- Qflow full end-to-end digital synthesis flow for ASIC designs☆215Updated 8 months ago