Alternatives and similar repositories for BAG_framework:

Users that are interested in BAG_framework are comparing it to the libraries listed below

• ALIGN-analoglayout / AnalogDetailedRouter
  Intel's Analog Detailed Router
  ☆38Updated 5 years ago
• USCPOSH / AMPSE
  This is the repository of IPs of the group in USC who is developing Analog Mixed-signal Parameter Search Engine (AMPSE). You can download…
  ☆24Updated last year
• johnkustin / bandgapReferenceCircuit
  repository for a bandgap voltage reference in SKY130 technology
  ☆35Updated 2 years ago
• ucb-art / BAG2_cds_ff_mpt
  BAG2 workspace for fake PDK (cds_ff_mpt)
  ☆54Updated 4 years ago
• magical-eda / MAGICAL-CIRCUITS
  Circuit release of the MAGICAL project
  ☆31Updated 5 years ago
• niftylab / laygo2
  LAYout with Gridded Objects v2
  ☆55Updated 3 weeks ago
• mabrains / PLL_design
  PLL Designs on Skywater 130nm MPW
  ☆20Updated last year
• ABKGroup / RosettaStone
  ☆23Updated 2 years ago
• vsdip / vsdsram_sky130
  ☆40Updated 2 years ago
• sgherbst / sky130-hello-world
  Minimal SKY130 example with self-checking LVS, DRC, and PEX
  ☆23Updated 4 years ago
• ShonTaware / SRAM_SKY130
  Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns
  ☆66Updated 3 years ago
• christoph-weiser / mpw6
  submission repository for efabless mpw6 shuttle
  ☆30Updated last year
• bluecheetah / bag
  BAG framework
  ☆40Updated 6 months ago
• ieee-ceda-datc / datc-rdf-Metrics4ML
  ☆28Updated 3 years ago
• The-OpenROAD-Project / asap7_pdk_r1p7
  ☆13Updated 7 months ago
• patrickschulz / openPCells
  Parametric layout generator for digital, analog and mixed-signal integrated circuits
  ☆52Updated last week
• ABKGroup / PROBE3.0
  ☆37Updated 10 months ago
• spider-tronix / Standard-Cell-Characterization
  Open Source tool to build liberty files and for Characterizing Standard Cells.
  ☆24Updated 4 years ago
• d-m-bailey / cvc
  CVC: Circuit Validity Checker. Check for errors in CDL netlist.
  ☆22Updated last month
• laurentc2 / Verilog2Spice
  Simple strutured VERILOG netlist to SPICE netlist translator
  ☆22Updated 2 years ago
• mabrains / Analog_blocks
  Design of Analog Blocks in Skywaters 130nm meeting corners: different flavors of OTA, BandGap, LDO.
  ☆26Updated 2 years ago
• ABKGroup / PROBE_SMT_AutoCell
  ☆17Updated last year
• StefanSchippers / xschem_sky130
  XSCHEM symbol libraries for the Google-Skywater 130nm process design kit.
  ☆60Updated 2 weeks ago
• ucdrstdenis / cdsAsync
  cdsAsync: An Asynchronous QDI VLSI Toolset & Schematic Library
  ☆25Updated 5 years ago
• Ravenslofty / librecell
  ☆20Updated 3 years ago
• iic-jku / Circuit-Designers-Etiquette
  A set of rules and recommendations for analog and digital circuit designers.
  ☆27Updated 3 months ago
• bmurmann / Ngspice-on-Colab
  Sandbox for experimenting with Ngspice and open PDKs in Google Colab
  ☆22Updated 8 months ago
• ChrisZonghaoLi / sky130_ldo_rl
  This repo contains the code that runs RL+GNN to optimize LDOs in SKY130 process.
  ☆35Updated 7 months ago
• shariethernet / Physical-Design-with-OpenLANE-using-SKY130-PDK
  This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…
  ☆43Updated 3 years ago
• asyncvlsi / AMC
  AMC: Asynchronous Memory Compiler
  ☆48Updated 4 years ago