Alternatives and similar repositories for BAG_framework

Users that are interested in BAG_framework are comparing it to the libraries listed below

• magical-eda / MAGICAL-CIRCUITS
  Circuit release of the MAGICAL project
  ☆40Updated 5 years ago
• StefanSchippers / xschem_sky130
  XSCHEM symbol libraries for the Google-Skywater 130nm process design kit.
  ☆66Updated 2 months ago
• stineje / CharLib
  Open-source repository for a standard-cell library characterizer using complete open-source tools
  ☆40Updated 4 months ago
• ALIGN-analoglayout / AnalogDetailedRouter
  Intel's Analog Detailed Router
  ☆39Updated 6 years ago
• bluecheetah / bag
  BAG framework
  ☆41Updated last year
• jaijeet / VAPP
  The Berkeley Verilog-A Parser and Processor
  ☆14Updated 8 years ago
• patrickschulz / openPCells
  Parametric layout generator for digital, analog and mixed-signal integrated circuits
  ☆63Updated this week
• niftylab / laygo2
  LAYout with Gridded Objects v2
  ☆65Updated 5 months ago
• parallaxsw / OpenSTA
  ☆94Updated last week
• ucb-art / BAG2_cds_ff_mpt
  BAG2 workspace for fake PDK (cds_ff_mpt)
  ☆59Updated 5 years ago
• laurentc2 / SKY130_for_KLayout
  KLayout technology files for Skywater SKY130
  ☆43Updated 2 years ago
• johnkustin / bandgapReferenceCircuit
  repository for a bandgap voltage reference in SKY130 technology
  ☆41Updated 2 years ago
• aziesemer / astran
  ASTRAN - Automatic Synthesis of Transistor Networks
  ☆65Updated 3 years ago
• pymtl / pymtl3-hardfloat
  PyMTL3 wrapper of the Berkeley Hardfloat IP
  ☆10Updated 2 years ago
• vsdip / vsdsram_sky130
  ☆43Updated 3 years ago
• USCPOSH / AMPSE
  This is the repository of IPs of the group in USC who is developing Analog Mixed-signal Parameter Search Engine (AMPSE). You can download…
  ☆25Updated 2 years ago
• ABKGroup / PROBE3.0
  ☆49Updated last year
• RTimothyEdwards / netgen
  Netgen complete LVS tool for comparing SPICE or verilog netlists
  ☆126Updated this week
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆51Updated 7 months ago
• The-OpenROAD-Project / TritonRoute
  UCSD Detailed Router
  ☆94Updated 4 years ago
• magical-eda / MAGICAL
  Machine Generated Analog IC Layout
  ☆260Updated last year
• lnis-uofu / LSOracle
  IDEA project source files
  ☆110Updated last month
• praharshapm / vsdmixedsignalflow
  This project describes how the PNR of an analog IP, 2:1 analog multiplexer is carried out by opensource EDA tools, Openlane. It also disc…
  ☆44Updated 4 years ago
• RTimothyEdwards / qrouter
  Qrouter detail router for digital ASIC designs
  ☆57Updated 2 weeks ago
• woset-workshop / woset-workshop.github.io
  Workshop on Open-Source EDA Technology (WOSET)
  ☆48Updated last year
• AsFigo / yoYoLint
  SystemVerilog RTL Linter for YoSys
  ☆21Updated last year
• efabless / chipignite-resources
  ☆84Updated 3 years ago
• jinwookjungs / datc_robust_design_flow
  DATC Robust Design Flow.
  ☆36Updated 5 years ago
• kunalg123 / vsdflow
  VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft the…
  ☆164Updated 2 years ago
• nickson-jose / vsdstdcelldesign
  This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…
  ☆75Updated 5 years ago