albaEDA / NirahLinks
Nirah is a project aimed at automatically wrapping verilator C++ models in python in order for high level, extendable control and verification of verilog systems.
☆12Updated 6 years ago
Alternatives and similar repositories for Nirah
Users that are interested in Nirah are comparing it to the libraries listed below
Sorting:
- USB virtual model in C++ for Verilog☆30Updated 7 months ago
- Generate symbols from HDL components/modules☆21Updated 2 years ago
- Examples and design pattern for VHDL verification☆15Updated 9 years ago
- FuseSoc Verification Automation☆22Updated 2 years ago
- A padring generator for ASICs☆25Updated 2 years ago
- Peripheral Component Interconnect has taken Express lane long ago, going for xGbps SerDes. Now (for the first time) in opensource on the …☆11Updated this week
- ☆22Updated 3 weeks ago
- Trying to verify Verilog/VHDL designs with formal methods and tools☆41Updated last year
- Tests to evaluate the support of VHDL 2008 and VHDL 2019 features☆30Updated 4 months ago
- Gate-level visualization generator for SKY130-based chip designs.☆19Updated 3 years ago
- ☆13Updated 5 years ago
- Extended and external tests for Verilator testing☆16Updated 2 weeks ago
- VHDLproc is a VHDL preprocessor☆24Updated 3 years ago
- An automatic clock gating utility☆48Updated last month
- A tool for merging the MyHDL workflow with Vivado☆20Updated 5 years ago
- ☆36Updated 2 years ago
- Proposal to define an XML-based logging format for outputs from EDA tools and logging libraries.☆14Updated this week
- Virtual development board for HDL design☆42Updated 2 years ago
- Library of reusable VHDL components☆28Updated last year
- ☆31Updated last year
- Small footprint and configurable Inter-Chip communication cores☆58Updated last week
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 2 years ago
- Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores☆51Updated last year
- Cross EDA Abstraction and Automation☆38Updated last week
- ☆26Updated last year
- USB 2.0 Device IP core using Migen with out-of-box AXI Slave Interface☆12Updated 7 years ago
- Specification of the Wishbone SoC Interconnect Architecture☆45Updated 3 years ago
- Automated Git mirror of Gaisler's GRLIB/Leon3 releases☆17Updated 2 months ago
- RISC-V 32-bit core for MCCI Catena 4710☆10Updated 5 years ago
- cocotb extension for nMigen☆16Updated 3 years ago