albaEDA / NirahLinks
Nirah is a project aimed at automatically wrapping verilator C++ models in python in order for high level, extendable control and verification of verilog systems.
☆12Updated 6 years ago
Alternatives and similar repositories for Nirah
Users that are interested in Nirah are comparing it to the libraries listed below
Sorting:
- RISC-V 32-bit core for MCCI Catena 4710☆10Updated 5 years ago
- Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores☆51Updated last year
- USB 2.0 Device IP core using Migen with out-of-box AXI Slave Interface☆12Updated 7 years ago
- A simple function to add wavedrom diagrams into an ipython notebook.☆24Updated 3 years ago
- Generate symbols from HDL components/modules☆21Updated 2 years ago
- USB virtual model in C++ for Verilog☆31Updated 9 months ago
- Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards☆45Updated this week
- cocotb extension for nMigen☆17Updated 3 years ago
- 🔍 Zoomable Waveform viewer for the Web☆43Updated 4 years ago
- A padring generator for ASICs☆25Updated 2 years ago
- This repository contains synthesizable examples which use the PoC-Library.☆38Updated 4 years ago
- Specification of the Wishbone SoC Interconnect Architecture☆45Updated 3 years ago
- ☆20Updated 3 years ago
- Peripheral Component Interconnect has taken Express lane long ago, going for xGbps SerDes. Now (for the first time) in opensource on the …☆13Updated this week
- Small footprint and configurable Inter-Chip communication cores☆60Updated last week
- Convert an image to a GDS format for inclusion in a zerotoasic project☆13Updated 3 years ago
- Virtual development board for HDL design☆42Updated 2 years ago
- sample VCD files☆37Updated last week
- Extended and external tests for Verilator testing☆16Updated this week
- Library of reusable VHDL components☆28Updated last year
- ☆22Updated 2 months ago
- The PicoBlaze-Library offers several PicoBlaze devices and code routines to extend a common PicoBlaze environment to a little System on a…☆36Updated 4 years ago
- Automated Git mirror of Gaisler's GRLIB/Leon3 releases☆17Updated last week
- wavedrom to verilog converter☆16Updated 3 years ago
- Atom Hardware IDE☆13Updated 4 years ago
- Gate-level visualization generator for SKY130-based chip designs.☆19Updated 3 years ago
- HDL tools layer for OpenEmbedded☆17Updated 8 months ago
- Ease the Life of Verification Engineers by helping them to analyze and understand failing simulation faster☆11Updated 3 years ago
- This is mainly a simulation library of xilinx primitives that are verilator compatible.☆33Updated last year
- Examples and design pattern for VHDL verification☆15Updated 9 years ago