albaEDA / NirahLinks
Nirah is a project aimed at automatically wrapping verilator C++ models in python in order for high level, extendable control and verification of verilog systems.
☆12Updated 6 years ago
Alternatives and similar repositories for Nirah
Users that are interested in Nirah are comparing it to the libraries listed below
Sorting:
- Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores☆51Updated 2 years ago
- USB virtual model in C++ for Verilog☆31Updated 9 months ago
- RISC-V 32-bit core for MCCI Catena 4710☆10Updated 6 years ago
- A simple function to add wavedrom diagrams into an ipython notebook.☆24Updated 3 years ago
- Small footprint and configurable Inter-Chip communication cores☆60Updated last month
- Virtual development board for HDL design☆42Updated 2 years ago
- cocotb extension for nMigen☆17Updated 3 years ago
- Extended and external tests for Verilator testing☆16Updated 2 weeks ago
- GUI editor for hardware description designs☆28Updated 2 years ago
- A padring generator for ASICs☆25Updated 2 years ago
- Generate symbols from HDL components/modules☆21Updated 2 years ago
- 🔍 Zoomable Waveform viewer for the Web☆44Updated 4 years ago
- ☆20Updated 3 years ago
- Examples and design pattern for VHDL verification☆15Updated 9 years ago
- USB 2.0 Device IP core using Migen with out-of-box AXI Slave Interface☆12Updated 7 years ago
- Automated Git mirror of Gaisler's GRLIB/Leon3 releases☆18Updated last month
- Digital Circuit rendering engine☆39Updated last week
- Peripheral Component Interconnect has taken Express lane long ago, going for xGbps SerDes. Now (for the first time) in opensource on the …☆13Updated this week
- Verilog+VHDL Hierarchy Management tool ( IDE ) wraps around Vim, runs in Linux terminal window.☆12Updated 8 years ago
- Open-source RHBD (Radiation Hardened by Design) Standard-Cell Library for SKY130☆8Updated 2 months ago
- Gate-level visualization generator for SKY130-based chip designs.☆20Updated 4 years ago
- LunaPnR is a place and router for integrated circuits☆47Updated 2 weeks ago
- LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled☆63Updated 3 weeks ago
- mantle library☆44Updated 2 years ago
- a project to check the FOSS synthesizers against vendors EDA tools☆12Updated 4 years ago
- VHDLproc is a VHDL preprocessor☆24Updated 3 years ago
- 🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.☆29Updated 2 years ago
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆30Updated last year
- Carrier for efabless Caravel chip used for Google/Skywater 130nm shuttle program.☆18Updated 3 years ago
- Specification of the Wishbone SoC Interconnect Architecture☆45Updated 3 years ago