albaEDA / NirahLinks
Nirah is a project aimed at automatically wrapping verilator C++ models in python in order for high level, extendable control and verification of verilog systems.
☆12Updated 6 years ago
Alternatives and similar repositories for Nirah
Users that are interested in Nirah are comparing it to the libraries listed below
Sorting:
- cocotb extension for nMigen☆17Updated 3 years ago
- Generate symbols from HDL components/modules☆21Updated 2 years ago
- USB virtual model in C++ for Verilog☆31Updated 8 months ago
- Peripheral Component Interconnect has taken Express lane long ago, going for xGbps SerDes. Now (for the first time) in opensource on the …☆13Updated 3 weeks ago
- This repository is no longer maintained. New repository is here(https://github.com/rggen/rggen).☆17Updated 5 years ago
- A simple function to add wavedrom diagrams into an ipython notebook.☆24Updated 3 years ago
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆30Updated 11 months ago
- USB 2.0 Device IP core using Migen with out-of-box AXI Slave Interface☆12Updated 7 years ago
- RISC-V 32-bit core for MCCI Catena 4710☆10Updated 5 years ago
- ☆22Updated last month
- Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores☆51Updated last year
- Extended and external tests for Verilator testing☆16Updated last month
- Examples and design pattern for VHDL verification☆15Updated 9 years ago
- 🔍 Zoomable Waveform viewer for the Web☆43Updated 4 years ago
- a project to check the FOSS synthesizers against vendors EDA tools☆12Updated 4 years ago
- Small footprint and configurable Inter-Chip communication cores☆59Updated last month
- 🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.☆29Updated 2 years ago
- FuseSoc Verification Automation☆22Updated 2 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 2 years ago
- Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…☆27Updated 4 months ago
- Proposal to define an XML-based logging format for outputs from EDA tools and logging libraries.☆14Updated last week
- A padring generator for ASICs☆25Updated 2 years ago
- Implementation of a SDRAM controller in MyHDL (http://www.myhdl.org/)☆21Updated 9 years ago
- Virtual development board for HDL design☆42Updated 2 years ago
- A configurable USB 2.0 device core☆31Updated 5 years ago
- GUI editor for hardware description designs☆28Updated last year
- 🕒 Static Timing Analysis diagram renderer☆13Updated last year
- Repo to help explain the different options users have for packaging.☆17Updated 3 years ago
- AXI Formal Verification IP☆20Updated 4 years ago
- ☆20Updated 3 years ago