Alternatives and similar repositories for linter-veriloghdl

Users that are interested in linter-veriloghdl are comparing it to the libraries listed below

• wavedrom / verilog

  View on GitHub
  wavedrom to verilog converter
  ☆17Sep 14, 2021Updated 4 years ago
• wmy367 / Radix-2-division

  View on GitHub
  unsigned Radix-2 SRT division,基2除法
  ☆16May 12, 2015Updated 10 years ago
• ydnatag / nmigen-cocotb

  View on GitHub
  cocotb extension for nMigen
  ☆17Feb 26, 2022Updated 3 years ago
• pytec8800 / pint_iverilog

  View on GitHub
  Project PLS is developed based on icarus iverilog and will compile verilog into a much faster optimized model.
  ☆13Nov 15, 2021Updated 4 years ago
• bobbl / rudolv

  View on GitHub
  RISC-V processor
  ☆32May 26, 2022Updated 3 years ago
• chipsalliance / f4pga-sdf-timing

  View on GitHub
  Python library for working Standard Delay Format (SDF) Timing Annotation files.
  ☆30Jul 12, 2024Updated last year
• AsFigo / svck

  View on GitHub
  ☆14May 24, 2025Updated 8 months ago
• shenki / exar-uart-driver

  View on GitHub
  Linux kernel driver for the Exar xr21v141x "vizzini" UART
  ☆10Jul 2, 2015Updated 10 years ago
• zilongwang123 / LeaVe

  View on GitHub
  A tool for checking the contract satisfaction for hardware designs
  ☆12Nov 4, 2025Updated 3 months ago
• FouriersCat / rex1168.github.io

  View on GitHub
  ☆13Apr 12, 2023Updated 2 years ago
• EECScat / MMCM_Dynamic-Reconfiguration

  View on GitHub
  This repository provides a method to dynamically change the clock output frequency, phase shift, and duty cycle of the mixed-mode clock m…
  ☆14Nov 4, 2020Updated 5 years ago
• ChrisBeaumont / oni

  View on GitHub
  Balance Calculator for Oxygen Not Included
  ☆11Jan 4, 2022Updated 4 years ago
• CoriolisSP / FuzzBtor2

  View on GitHub
  Random Generator of Btor2 Files
  ☆10Sep 2, 2023Updated 2 years ago
• wzc810049078 / SRT-4-DIVISION

  View on GitHub
  RADIX-4 SRT division
  ☆12Oct 31, 2019Updated 6 years ago
• bespoke-silicon-group / bsg_sv2v

  View on GitHub
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆44Apr 13, 2023Updated 2 years ago
• bohanw / jpeg_comp_verilog

  View on GitHub
  JPEG Compression RTL implementation
  ☆11Aug 19, 2017Updated 8 years ago
• suraj-srinivas / Huffman-encoder

  View on GitHub
  Huffman encoder
  ☆10Sep 8, 2013Updated 12 years ago
• felixheld / photonSDI

  View on GitHub
  photonSDI - an open source SDI core
  ☆10May 26, 2021Updated 4 years ago
• Obeisance / Daft_LotusT4_OBD

  View on GitHub
  A daft implementation of an ISO-9141 OBD-II logger
  ☆10Sep 22, 2025Updated 4 months ago
• mcci-catena / catena-riscv32-fpga

  View on GitHub
  RISC-V 32-bit core for MCCI Catena 4710
  ☆10Jul 31, 2019Updated 6 years ago
• mlocati / jsgettext

  View on GitHub
  Online tools to work with gettext .po, .mo and .pot files
  ☆11May 31, 2018Updated 7 years ago
• daveshah1 / hilotof

  View on GitHub
  HiLoTOF -- Hardware-in-the-Loop Test framework for Open FPGAs
  ☆13Feb 9, 2019Updated 7 years ago
• freecores / divider

  View on GitHub
  Hardware Division Units
  ☆10Jul 17, 2014Updated 11 years ago
• byuccl / bfat

  View on GitHub
  Bitstream Fault Analysis Tool
  ☆15Jul 17, 2023Updated 2 years ago
• jinwookjungs / datc_robust_design_flow

  View on GitHub
  DATC Robust Design Flow.
  ☆36Jan 21, 2020Updated 6 years ago
• cfelton / minnesota

  View on GitHub
  A collection of HDL cores written in MyHDL.
  ☆12Oct 28, 2015Updated 10 years ago
• YosysHQ / sby-gui

  View on GitHub
  GUI for SymbiYosys
  ☆17Oct 13, 2025Updated 4 months ago
• UGent-HES / tlut_flow

  View on GitHub
  TLUT tool flow for parameterised configurations for FPGAs
  ☆16Aug 5, 2024Updated last year
• space-tudelft / cacd

  View on GitHub
  Space CACD
  ☆11Oct 16, 2019Updated 6 years ago
• Wint3rmute / neural-network-car

  View on GitHub
  C# Implementation of a simple neural network driving a car
  ☆11Jun 29, 2019Updated 6 years ago
• MyersResearchGroup / ATACS

  View on GitHub
  ☆10Jun 4, 2021Updated 4 years ago
• lip6 / alliance

  View on GitHub
  Alliance VLSI CAD Tools (LIP6)
  ☆19Dec 11, 2025Updated 2 months ago
• Obijuan / iceFactory

  View on GitHub
  A Javascript library for generating blocks for the ICEstudio FPGA development environment
  ☆10Jul 31, 2018Updated 7 years ago
• riktw / SoftcoreComparisons

  View on GitHub
  The code for an FPGA softcore comparison
  ☆11Jun 21, 2020Updated 5 years ago
• verilog-to-routing / libsdcparse

  View on GitHub
  ☆12Feb 6, 2026Updated last week
• xobs / spibone

  View on GitHub
  Wishbone bridge over SPI
  ☆11Nov 13, 2019Updated 6 years ago
• chc-comp / chc-tools

  View on GitHub
  Tools for manipulating CHC and related files
  ☆15Apr 21, 2023Updated 2 years ago
• YosysHQ / prjtrellis-db

  View on GitHub
  Project Trellis database
  ☆14Sep 15, 2025Updated 5 months ago
• antmicro / usb-test-suite-cocotb-usb

  View on GitHub
  ☆10Apr 8, 2021Updated 4 years ago