Alternatives and similar repositories for linter-veriloghdl:

Users that are interested in linter-veriloghdl are comparing it to the libraries listed below

• YosysHQ / yosys-bench
  Benchmarks for Yosys development
  ☆23Updated 5 years ago
• jameshanlon / netlist-paths
  A library and command-line tool for querying a Verilog netlist.
  ☆26Updated 2 years ago
• efabless / sky130_sram_macros_old
  ☆36Updated 2 years ago
• AsFigo / yoYoLint
  SystemVerilog RTL Linter for YoSys
  ☆19Updated 3 months ago
• mattvenn / multi_project_tools
  tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles
  ☆35Updated 2 years ago
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆39Updated last year
• vmunoz82 / sudoku-challenge
  Solving Sudokus using open source formal verification tools
  ☆16Updated 2 years ago
• b224hisl / rioschip
  ☆33Updated 2 years ago
• efabless / caravel_mgmt_soc_litex
  https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/
  ☆27Updated last month
• thesourcerer8 / StdCellLib
  LibreSilicon's Standard Cell Library Generator
  ☆18Updated 9 months ago
• XedaHQ / xeda
  Cross EDA Abstraction and Automation
  ☆36Updated this week
• YosysHQ / yosys-tests
  Collection of test cases for Yosys
  ☆18Updated 3 years ago
• chipsalliance / f4pga-sdf-timing
  Python library for working Standard Delay Format (SDF) Timing Annotation files.
  ☆28Updated 7 months ago
• lnis-uofu / TIGFET-10nm-PDK
  An open source PDK using TIGFET 10nm devices.
  ☆47Updated 2 years ago
• PyHDI / ipgen
  IP-core package generator for AXI4/Avalon
  ☆22Updated 6 years ago
• westonb / open-pmic
  A current mode buck converter on the SKY130 PDK
  ☆27Updated 3 years ago
• chipsalliance / python-fpga-interchange
  Python interface to FPGA interchange format
  ☆41Updated 2 years ago
• The-OpenROAD-Project / megaboom
  ☆24Updated 3 weeks ago
• sgherbst / svinst
  Determines the modules declared and instantiated in a SystemVerilog file
  ☆43Updated 4 months ago
• gsomlo / yoloRISC
  A RocketChip rv64imac blinky for yosys/nextpnr/trellis & the Lattice ECP5 fpga
  ☆26Updated 5 years ago
• efabless / caravel-lite
  ☆15Updated 3 months ago
• idea-fasoc / fasoc
  ☆53Updated last year
• FPGA-Research / eFPGA---RTL-to-GDS-with-SKY130
  This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk
  ☆27Updated 3 years ago
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆74Updated this week
• verilator / verilator_ext_tests
  Extended and external tests for Verilator testing
  ☆16Updated this week
• antmicro / cocotb-verilator-build
  ☆26Updated last year
• YosysHQ / padring
  A padring generator for ASICs
  ☆25Updated last year
• mohamed / fsm2sv
  SystemVerilog FSM generator
  ☆27Updated 9 months ago
• umarcor / osvb
  Open Source Verification Bundle for VHDL and System Verilog
  ☆43Updated last year
• vsdip / vsdStdCellCharacterizer_sky130
  ☆20Updated 3 years ago