Alternatives and similar repositories for meta-hdl:

Users that are interested in meta-hdl are comparing it to the libraries listed below

• enjoy-digital / liteiclink
  Small footprint and configurable Inter-Chip communication cores
  ☆55Updated last month
• litex-hub / litespi
  Small footprint and configurable SPI core
  ☆41Updated last month
• antmicro / usb-test-suite-build
  Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores
  ☆50Updated last year
• GuzTech / misato
  RISC-V Processor written in Amaranth HDL
  ☆36Updated 3 years ago
• m-labs / nmigen-soc
  System on Chip toolkit for nMigen
  ☆19Updated 4 years ago
• www-asics-ws / usb1_device
  USB 1.1 Device IP Core
  ☆18Updated 7 years ago
• xobs / lxbuildenv
  Simplified environment for litex
  ☆14Updated 4 years ago
• mattvenn / ws2812-core
  verilog core for ws2812 leds
  ☆32Updated 3 years ago
• Blinkinlabs / QL-EOS-S3-breakout
  ☆12Updated 3 years ago
• xobs / valentyusb
  USB Full-Speed core written in migen/LiteX
  ☆12Updated 5 years ago
• ydnatag / nmigen-cocotb
  cocotb extension for nMigen
  ☆16Updated 2 years ago
• lambdaconcept / lambdaUSB
  A configurable USB 2.0 device core
  ☆30Updated 4 years ago
• butterstick-fpga / butterstick-bootloader
  LiteX project for the ButterStick bootloader
  ☆13Updated last year
• f32c / tools
  ULX2S / ULX3S FPGA JTAG programmer & tools (Lattice XP2 / ECP5)
  ☆22Updated 3 months ago
• daveshah1 / flow-examples
  Misc open FPGA flow examples
  ☆8Updated 5 years ago
• stnolting / fpga_torture
  🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.
  ☆29Updated 2 years ago
• micro-FPGA / CRUVI
  CRUVI Standard Specifications
  ☆17Updated 9 months ago
• dbhi / vboard
  Virtual development board for HDL design
  ☆40Updated last year
• whitequark / icefloorplan
  iCE40 floorplan viewer
  ☆24Updated 6 years ago
• fusesoc / sd_device
  SD device emulator from ProjectVault
  ☆15Updated 5 years ago
• m-labs / VexRiscv-verilog
  Using VexRiscv without installing Scala
  ☆37Updated 3 years ago
• wyvernSemi / usbModel
  USB virtual model in C++ for Verilog
  ☆29Updated 4 months ago
• icebreaker-fpga / icebreaker-amaranth-examples
  This repository contains iCEBreaker examples for Amaranth HDL.
  ☆38Updated last year
• azonenberg / antikernel-ipcores
  FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations
  ☆62Updated this week
• tomverbeure / ecp5_jtag
  Use ECP5 JTAG port to interact with user design
  ☆26Updated 3 years ago
• YosysHQ / padring
  A padring generator for ASICs
  ☆25Updated last year
• lawrie / tiny_ram_soc
  Picorv32 SoC that uses only BRAM, not flash memory
  ☆12Updated 6 years ago
• gatecat / meowality
  ☆15Updated last year
• litex-hub / litehyperbus
  Small footprint and configurable HyperBus core
  ☆11Updated 2 years ago