nathanrossi / meta-hdl
HDL tools layer for OpenEmbedded
☆17Updated 3 weeks ago
Related projects ⓘ
Alternatives and complementary repositories for meta-hdl
- System on Chip toolkit for nMigen☆20Updated 4 years ago
- Small footprint and configurable Inter-Chip communication cores☆54Updated last month
- Misc open FPGA flow examples☆8Updated 4 years ago
- Cross compile FPGA tools☆22Updated 3 years ago
- Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores☆50Updated last year
- Small footprint and configurable SPI core☆39Updated this week
- RISC-V Processor written in Amaranth HDL☆31Updated 2 years ago
- Picorv32 SoC that uses only BRAM, not flash memory☆12Updated 5 years ago
- Utilities for the ECP5 FPGA☆18Updated 3 years ago
- This repository contains iCEBreaker examples for Amaranth HDL.☆36Updated last year
- Using VexRiscv without installing Scala☆36Updated 3 years ago
- Drop In USB CDC ACM core for iCE40 FPGA☆33Updated 3 years ago
- 🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.☆29Updated 2 years ago
- A padring generator for ASICs☆22Updated last year
- Altera MAX V bitstream documentation -- CLEANUP PENDING☆19Updated 4 years ago
- Use ECP5 JTAG port to interact with user design☆24Updated 3 years ago
- There are many RISC V projects on iCE40. This one is mine.☆13Updated 4 years ago
- XVCD implementation for ANITA. Note that "ftdi_xvc_core.c" is a generic libftdi-based MPSSE XVC handler, and is awesome.☆18Updated 4 years ago
- nextpnr portable FPGA place and route tool☆12Updated 3 years ago
- USB 1.1 Device IP Core☆18Updated 7 years ago
- ☆10Updated 6 years ago
- Tool to parse yosys and nextpnr logfiles to then plot LUT, flip-flop and maximum frequency stats as your project progresses.☆19Updated last year
- A reconfigurable logic circuit made of identical rotatable tiles.☆19Updated 2 years ago
- iCE40 floorplan viewer☆24Updated 6 years ago
- Wishbone bridge over SPI☆11Updated 4 years ago
- USB Full-Speed core written in migen/LiteX☆12Updated 5 years ago
- Open-source CSI-2 receiver for Xilinx UltraScale parts☆35Updated 5 years ago
- Simplified environment for litex☆13Updated 4 years ago