Alternatives and similar repositories for corner_stitch

Users that are interested in corner_stitch are comparing it to the libraries listed below

• shininglion / rectilinear_spanning_graph
  This library contains rectilinear spanning graph construction, finding minimum spanning tree and an implementation of binary search tree
  ☆10Updated 9 years ago
• The-OpenROAD-Project / OpenDB
  Database and Tool Framework for EDA
  ☆115Updated 4 years ago
• The-OpenROAD-Project / TritonMacroPlace
  Macro placement tool for OpenROAD flow
  ☆23Updated 4 years ago
• limbo018 / OpenMPL
  An open multiple patterning framework
  ☆78Updated last year
• luckyrantanplan / nthu-route
  VLSI EDA Global Router
  ☆73Updated 7 years ago
• Daikon-Sun / Physical-Design-for-Nanometer-ICs
  Assignments of Physical Design for Nanometer ICs (Spring 2017, Prof. Yao-Wen Chang)
  ☆41Updated 6 years ago
• The-OpenROAD-Project-Attic / FastRoute
  LEF/DEF-based port of Iowa State's open-source FastRoute 4.1
  ☆56Updated 4 years ago
• limbo018 / Limbo
  Library for VLSI CAD Design Useful parsers and solvers' api are implemented.
  ☆172Updated 2 months ago
• chengengjie / salt
  Steiner Shallow-Light Tree for VLSI Routing
  ☆52Updated last year
• EDDRSoftware / gdsFileParser
  This library is a low level parser for the GDSII file format.
  ☆35Updated 8 years ago
• OpenTimer / Parser-SPEF
  A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).
  ☆56Updated 2 years ago
• aziesemer / astran
  ASTRAN - Automatic Synthesis of Transistor Networks
  ☆62Updated 3 years ago
• ashtanyuk / GDSII-Links
  GDSII file format links
  ☆13Updated 5 years ago
• The-OpenROAD-Project / SA-PCB
  Annealing-based PCB placement tool
  ☆39Updated 5 years ago
• lsils / mockturtle
  C++ logic network library
  ☆240Updated 3 weeks ago
• AUCOHL / OGRE
  Global Router Built for ICCAD Contest 2019
  ☆31Updated 5 years ago
• The-OpenROAD-Project / PDNSim
  Power grid analysis
  ☆19Updated 4 years ago
• eigenpi / mcf_solver
  Multicommodity Flow: efficient C++ implementation of a polynomial time approximation algorithm
  ☆22Updated 9 years ago
• rachelselinar / ReGDS-Logic-Gate-Extraction
  A custom C++ routine to identify logic gates in the layout extracted netlist (SPICE) of digital circuits and generate gate-level Verilog …
  ☆31Updated 10 months ago
• RsynTeam / rsyn-x
  Rsyn – An Extensible Physical Synthesis Framework
  ☆127Updated last year
• cuhk-eda / dr-cu
  Dr. CU, VLSI Detailed Routing Tool Developed by CUHK
  ☆135Updated 2 years ago
• zslwyuan / AMF-Placer
  AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…
  ☆105Updated last year
• UMN-EDA / BeGAN-benchmarks
  ☆25Updated 2 years ago
• Coloquinte / Coloquinte_placement
  An analytical VLSI placer
  ☆28Updated 3 years ago
• cuhk-eda / Xplace
  Xplace 3.0: An Extremely Fast, Extensible and Deterministic Placement Framework with Detailed-Routability and Timing Optimization
  ☆132Updated last month
• The-OpenROAD-Project / PcbRouter
  ☆31Updated 4 years ago
• verilog-to-routing / tatum
  Tatum: A Fast, Flexible Static Timing Analysis (STA) Engine for Digital Circuits
  ☆62Updated last year
• The-OpenROAD-Project-Attic / ioPlacer
  IO and Pin Placer for Floorplan-Placement Subflow
  ☆22Updated 4 years ago
• The-OpenROAD-Project / Birds-of-a-Feather-Open-Source-Academic-EDA-Software
  Welcome to Birds-of-a-Feather: Open-Source-Academic-EDA-Software !
  ☆13Updated 6 years ago
• scale-lab / OpenPhySyn
  EDA physical synthesis optimization kit
  ☆59Updated last year