sin-x / HackerRank-FPGA-InterviewLinks
HackerRank test solutions for FPGA engineer interview at Optiver
☆12Updated 5 years ago
Alternatives and similar repositories for HackerRank-FPGA-Interview
Users that are interested in HackerRank-FPGA-Interview are comparing it to the libraries listed below
Sorting:
- SystemVerilog Tutorial☆176Updated this week
- 2D Systolic Array Multiplier☆20Updated last year
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆117Updated last week
- Synthesizable RTL-Based video stream Convolutional Neural Network ( non HLS )☆64Updated 11 months ago
- Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…☆63Updated last year
- This repo provide an index of VLSI content creators and their materials☆157Updated last year
- Curriculum for a university course to teach chip design using open source EDA tools☆110Updated last year
- ☆45Updated 2 years ago
- Gain an introductory knowledge to the basics of SoC design and key skills required to implement a simple SoC on an FPGA, and write embedd…☆141Updated this week
- Verilog digital signal processing components☆156Updated 2 years ago
- An overview of TL-Verilog resources and projects☆82Updated 6 months ago
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆112Updated last year
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆140Updated last week
- This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve…☆80Updated last year
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆176Updated 10 months ago
- A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.☆136Updated 5 years ago
- ☆227Updated 2 months ago
- A demo system for Ibex including debug support and some peripherals☆78Updated 4 months ago
- Design, implement, and test an Arm Cortex-A-based SoCs on FPGA hardware using functional specifications, standard hardware description an…☆113Updated this week
- A huge collection of VHDL/Verilog open-source IP cores scraped from the web☆118Updated 9 years ago
- This XUP course provides an introduction to embedded system design on Zynq using the Xilinx Vivado software suite.☆86Updated 2 years ago
- Altera Advanced Synthesis Cookbook 11.0☆107Updated 2 years ago
- Basic RISC-V Test SoC☆146Updated 6 years ago
- Introductory course into static timing analysis (STA).☆97Updated 3 months ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆72Updated 9 months ago
- An AXI4 crossbar implementation in SystemVerilog☆175Updated last month
- Verilog/SystemVerilog Guide☆73Updated last year
- This is a verilog implementation of 4x4 systolic array multiplier☆60Updated 4 years ago
- Implementing Different Adder Structures in Verilog☆73Updated 6 years ago
- Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy mach…☆156Updated last year