sin-x / HackerRank-FPGA-Interview
HackerRank test solutions for FPGA engineer interview at Optiver
☆9Updated 4 years ago
Related projects ⓘ
Alternatives and complementary repositories for HackerRank-FPGA-Interview
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆54Updated 3 weeks ago
- ☆53Updated last year
- SystemVerilog Tutorial☆114Updated 11 months ago
- Introductory course into static timing analysis (STA).☆66Updated 3 weeks ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆148Updated last week
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆68Updated 11 months ago
- Altera Advanced Synthesis Cookbook 11.0☆93Updated last year
- Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…☆46Updated 7 months ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆63Updated 3 years ago
- Basic RISC-V Test SoC☆104Updated 5 years ago
- Two Level Cache Controller implementation in Verilog HDL☆36Updated 4 years ago
- This is a tutorial on standard digital design flow☆73Updated 3 years ago
- Mathematical Functions in Verilog☆86Updated 3 years ago
- An overview of TL-Verilog resources and projects☆72Updated 8 months ago
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆50Updated 2 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆59Updated last month
- This repo provide an index of VLSI content creators and their materials☆136Updated 3 months ago
- Xilinx AXI VIP example of use☆32Updated 3 years ago
- This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve…☆69Updated last year
- EE 260 Winter 2017: Advanced VLSI Design☆59Updated 7 years ago
- Pipelined RISC-V RV32I Core in Verilog☆36Updated last year
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆27Updated 2 years ago
- Synthesizable RTL-Based video stream Convolutional Neural Network ( non HLS )☆48Updated 2 weeks ago
- Implementing Different Adder Structures in Verilog☆60Updated 5 years ago
- This is full tutorial of UVM (Universal Verification Methodology) for a simple ALU unit☆18Updated 6 years ago
- ☆120Updated 2 years ago
- ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen☆151Updated 4 years ago
- This repository contains all the contents studied and created during the Advanced Physical Design Workshop using OpenLANE and SKY130 PDK☆34Updated 2 years ago
- This repository documents the learning from VSD "RTL Design Using Verilog With SKY130 Technology" workshop☆32Updated 3 years ago
- Generic Register Interface (contains various adapters)☆100Updated 2 months ago