sin-x / HackerRank-FPGA-Interview
HackerRank test solutions for FPGA engineer interview at Optiver
☆8Updated 4 years ago
Related projects: ⓘ
- SystemVerilog Tutorial☆111Updated 9 months ago
- Altera Advanced Synthesis Cookbook 11.0☆90Updated last year
- ☆117Updated 2 years ago
- 32-bit 5-Stage Pipelined RISC V RV32I Core☆26Updated 2 months ago
- Simple cache design implementation in verilog☆40Updated 10 months ago
- ☆15Updated last year
- The project is about building an 8-row by 8-bit 6T SRAM memory array, & a 3-to-8 decoder that's used to access the SRAM array. The layout…☆58Updated 2 years ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆136Updated last year
- Two Level Cache Controller implementation in Verilog HDL☆31Updated 4 years ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆29Updated last month
- An AXI4 crossbar implementation in SystemVerilog☆112Updated 3 months ago
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆46Updated 2 years ago
- ☆49Updated 11 months ago
- IEEE 754 floating point unit in Verilog☆122Updated 8 years ago
- Mathematical Functions in Verilog☆82Updated 3 years ago
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆65Updated 5 years ago
- IC implementation of Systolic Array for TPU☆137Updated 6 months ago
- Verilog HDL files☆83Updated 3 months ago
- Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in …☆117Updated 2 years ago
- AXI4 and AXI4-Lite interface definitions☆82Updated 4 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆62Updated last year
- DDR2 memory controller written in Verilog☆72Updated 12 years ago
- This XUP course provides an introduction to embedded system design on Zynq using the Xilinx Vivado software suite.☆76Updated last year
- ai_accelerator_basic_for_student (no solve)☆10Updated 4 years ago
- IEEE 754 floating point library in system-verilog and vhdl☆53Updated 3 months ago
- Introductory course into static timing analysis (STA).☆54Updated 5 months ago
- Various RTL design blocks along with verification testbenches with SVAs. Designed using SystemVerilog☆23Updated 2 years ago
- This is a tutorial on standard digital design flow☆71Updated 3 years ago
- This repository hosts the code for an FPGA based accelerator for convolutional neural networks☆114Updated 3 months ago
- An Open Workflow to Build Custom SoCs and run Deep Models at the Edge☆58Updated last month