Alternatives and similar repositories for HackerRank-FPGA-Interview

Users that are interested in HackerRank-FPGA-Interview are comparing it to the libraries listed below

• ARC-Lab-UF / sv-tutorial
  SystemVerilog Tutorial
  ☆178Updated this week
• AngeloJacobo / RISC-V
  Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
  ☆113Updated last year
• aignacio / ravenoc
  RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
  ☆179Updated 11 months ago
• TL-X-org / TL-V_Projects
  An overview of TL-Verilog resources and projects
  ☆81Updated 7 months ago
• MahmouodMagdi / Clock-Domain-Crossing-Synchronizers
  Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…
  ☆63Updated last year
• brabect1 / sta_basics_course
  Introductory course into static timing analysis (STA).
  ☆98Updated 3 months ago
• amradel2020 / vlsi_linkedin_index
  This repo provide an index of VLSI content creators and their materials
  ☆160Updated last year
• shivanishah269 / risc-v-core
  This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve…
  ☆81Updated 2 years ago
• lowRISC / ibex-demo-system
  A demo system for Ibex including debug support and some peripherals
  ☆78Updated 4 months ago
• thomasrussellmurphy / stx_cookbook
  Altera Advanced Synthesis Cookbook 11.0
  ☆108Updated 2 years ago
• snbk001 / Verilog-Design-Examples
  Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy mach…
  ☆159Updated last year
• ultraembedded / riscv_soc
  Basic RISC-V Test SoC
  ☆153Updated 6 years ago
• raysalemi / Python4RTLVerification
  ☆166Updated 3 years ago
• tms4517 / 2D-Systolic-Array-Multiplier
  2D Systolic Array Multiplier
  ☆20Updated last year
• nishthaparashar / Floating-Point-ALU-in-Verilog
  32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.
  ☆92Updated 6 years ago
• jasonlin316 / RISC-V-CPU
  A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.
  ☆136Updated 5 years ago
• Xilinx / Vivado-Design-Tutorials
  ☆234Updated 2 months ago
• asinghani / open-eda-course
  Curriculum for a university course to teach chip design using open source EDA tools
  ☆111Updated 2 years ago
• alexforencich / verilog-dsp
  Verilog digital signal processing components
  ☆158Updated 3 years ago
• arm-university / VLSI-Fundamentals-Education-Kit
  Gain an understanding of the fundamentals of Very Large-Scale Integration (VLSI), including how the theories and concepts can be applied …
  ☆273Updated 5 months ago
• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆72Updated 10 months ago
• danshanley / FPU
  IEEE 754 floating point unit in Verilog
  ☆148Updated 9 years ago
• AngeloJacobo / FPGA_Book_Experiments
  My completed projects from "FPGA Prototyping by Verilog Examples" book by Pong P. Chu
  ☆151Updated 4 years ago
• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆177Updated last month
• RClabiisc / I2SRV32-S-v1
  Reconfigurable Computing Lab, DESE, Indian Institiute of Science
  ☆30Updated 3 years ago
• raulbehl / 100DaysOfRTL
  100 Days of RTL
  ☆402Updated last year
• ash-olakangal / RISC-V-Processor
  Verilog implementation of multi-stage 32-bit RISC-V processor
  ☆134Updated 4 years ago
• ARC-Lab-UF / intel-training-modules
  ☆44Updated 2 years ago
• iammituraj / pequeno_riscv
  Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.
  ☆119Updated 3 weeks ago
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆231Updated this week