sin-x / HackerRank-FPGA-InterviewLinks
HackerRank test solutions for FPGA engineer interview at Optiver
☆10Updated 5 years ago
Alternatives and similar repositories for HackerRank-FPGA-Interview
Users that are interested in HackerRank-FPGA-Interview are comparing it to the libraries listed below
Sorting:
- SystemVerilog Tutorial☆166Updated 3 months ago
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆104Updated last year
- Curriculum for a university course to teach chip design using open source EDA tools☆107Updated last year
- This repo provide an index of VLSI content creators and their materials☆156Updated last year
- An overview of TL-Verilog resources and projects☆81Updated 5 months ago
- eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V☆211Updated last month
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆112Updated last week
- Basic RISC-V Test SoC☆140Updated 6 years ago
- Introductory course into static timing analysis (STA).☆97Updated last month
- Gain an understanding of the fundamentals of Very Large-Scale Integration (VLSI), including how the theories and concepts can be applied …☆265Updated 3 months ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆174Updated 9 months ago
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆135Updated 2 weeks ago
- Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy mach…☆152Updated last year
- mflowgen -- A Modular ASIC/FPGA Flow Generator☆259Updated last month
- ☆164Updated 2 years ago
- A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.☆133Updated 5 years ago
- IEEE 754 floating point unit in Verilog☆145Updated 9 years ago
- Verilog digital signal processing components☆151Updated 2 years ago
- Verilog implementation of multi-stage 32-bit RISC-V processor☆120Updated 4 years ago
- A demo system for Ibex including debug support and some peripherals☆76Updated 2 months ago
- 100 Days of RTL☆390Updated last year
- The project is about building an 8-row by 8-bit 6T SRAM memory array, & a 3-to-8 decoder that's used to access the SRAM array. The layout…☆75Updated 3 years ago
- Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…☆63Updated last year
- A Fast, Low-Overhead On-chip Network☆221Updated last month
- My completed projects from "FPGA Prototyping by Verilog Examples" book by Pong P. Chu☆143Updated 4 years ago
- ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen☆182Updated 5 years ago
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.☆75Updated last year
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆30Updated 3 years ago
- Verilog/SystemVerilog Guide☆72Updated last year
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆68Updated 8 months ago