Alternatives and similar repositories for fpga_labs_fa22

Users that are interested in fpga_labs_fa22 are comparing it to the libraries listed below

• schoeberl / chisel-lab
  Lab exercises for Chisel in the digital electronics 2 course at DTU
  ☆206Updated 2 months ago
• kaitoukito / Integrated-Circuit-Textbooks
  Collect some IC textbooks for learning.
  ☆151Updated 3 years ago
• jasonlin316 / RISC-V-CPU
  A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.
  ☆132Updated 5 years ago
• Dazhuzhu-github / systolic-array
  verilog实现TPU中的脉动阵列计算卷积的module
  ☆129Updated 3 months ago
• OSCPU / yosys-sta
  ☆78Updated 3 months ago
• wuzeyou / Multiplier16X16
  Classic Booth Code, Wallace Tree, and SquareRoot Carry Select Adder
  ☆118Updated 12 years ago
• github-3rr0r / RV32ISC
  A RISC-V RV32I ISA Single Cycle CPU
  ☆25Updated 2 months ago
• Evensgn / RISC-V-CPU
  RISC-V CPU with 5-stage pipeline, implemented in Verilog HDL.
  ☆297Updated 7 years ago
• OSCPU / ysyxSoC
  ☆86Updated this week
• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆166Updated last month
• EECS150 / fpga_labs_sp22
  ☆30Updated 3 years ago
• Yawei-Ding / ysyx_riscv64_cpu
  ☆68Updated 2 years ago
• abdelazeem201 / Systolic-array-implementation-in-RTL-for-TPU
  IC implementation of Systolic Array for TPU
  ☆264Updated 9 months ago
• BIGWJZ / VLSI-DSP-Review
  ☆71Updated 5 years ago
• OpenXiangShan / XS-Verilog-Library
  ☆43Updated 3 years ago
• RV-BOSC / OpenNoC
  ☆182Updated last month
• shawn110285 / Cookabarra
  a training-target implementation of rv32im, designed to be simple and easy to understand
  ☆60Updated 3 years ago
• karthisugumar / CSE240D-Hierarchical_Mesh_NoC-Eyeriss_v2
  A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…
  ☆164Updated 5 years ago
• hyf6661669 / Synopsys-Documents
  Some useful documents of Synopsys
  ☆78Updated 3 years ago
• Xilinx / xup_high_level_synthesis_design_flow
  AMD University Program HLS tutorial
  ☆99Updated 9 months ago
• peilin-chen / Zhulong-RISCV-CPU
  CPU Design Based on RISCV ISA
  ☆118Updated last year
• erihsu / INT_FP_MAC
  INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.
  ☆104Updated 4 years ago
• nishthaparashar / Floating-Point-ALU-in-Verilog
  32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.
  ☆89Updated 6 years ago
• schoeberl / chisel-examples
  Chisel examples and code snippets
  ☆257Updated 3 years ago
• wataru030-XIAOHEI / My-RISCV64-CORE-writing
  一生一芯 ， ysyx ， npc . the repo of the YSYX project . a riscv-64 CPU . writing .
  ☆31Updated 3 years ago
• RoyanTuscano / -TAGE-based-Predictor-Verilog-Code
  Verilog Implementation of TAGE based predictor by Andre Seznec and Pierre Michaud
  ☆20Updated 7 years ago
• huangxc6 / E203_CNN_Genesys2
  Final Project of Software_Hardware_Co-Design_24Spring. FPGA-based RISC-V+ Convolutional Acceleration Unit.
  ☆19Updated last year
• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆51Updated 3 years ago
• ysyx-ta / ysyx-summer-readings
  ☆66Updated last year
• bol-edu / 2022-fall-ntu
  ☆33Updated 10 months ago