EECS150 / fpga_labs_fa22Links
☆22Updated 3 years ago
Alternatives and similar repositories for fpga_labs_fa22
Users that are interested in fpga_labs_fa22 are comparing it to the libraries listed below
Sorting:
- Collect some IC textbooks for learning.☆168Updated 3 years ago
- verilog实现TPU中的脉动阵列计算卷积的module☆138Updated 5 months ago
- ☆70Updated 2 years ago
- 一生一芯 , ysyx , npc . the repo of the YSYX project . a riscv-64 CPU . writing .☆32Updated 3 years ago
- ☆33Updated last year
- Lab exercises for Chisel in the digital electronics 2 course at DTU☆212Updated 5 months ago
- AMD University Program HLS tutorial☆118Updated last year
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆174Updated 5 years ago
- A verilog implementation for Network-on-Chip☆77Updated 7 years ago
- ☆44Updated 3 years ago
- Small-scale Tensor Processing Unit built on an FPGA☆207Updated 6 years ago
- Some useful documents of Synopsys☆90Updated 4 years ago
- some knowleage about SystemC/TLM etc.☆26Updated 2 years ago
- ☆84Updated 6 months ago
- ai_accelerator_basic_for_student (no solve)☆13Updated 5 years ago
- My implementation of an FPGA Deep Neural Network Hardware Accelerator, moved from my bitbucket☆26Updated 6 years ago
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆116Updated 3 months ago
- ☆31Updated 3 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆105Updated 5 years ago
- IC implementation of Systolic Array for TPU☆293Updated last year
- An AXI4 crossbar implementation in SystemVerilog☆178Updated 2 months ago
- ☆41Updated 4 years ago
- This repository hosts the code for an FPGA based accelerator for convolutional neural networks☆168Updated last year
- RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni☆133Updated 7 years ago
- ☆204Updated 4 months ago
- A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.☆138Updated 5 years ago
- Two Level Cache Controller implementation in Verilog HDL☆53Updated 5 years ago
- Convolutional accelerator kernel, target ASIC & FPGA☆232Updated 2 years ago
- High Level Synthesis of a trained Convolutional Neural Network for handwritten digit recongnition.☆41Updated last year
- 32-bit 5-Stage Pipelined RISC V RV32I Core☆55Updated last year