Alternatives and similar repositories for 100DaysOfRTL

Users that are interested in 100DaysOfRTL are comparing it to the libraries listed below

• amradel2020 / vlsi_linkedin_index
  This repo provide an index of VLSI content creators and their materials
  ☆157Updated last year
• Ummidichandrika / RTL-Examples
  ☆10Updated last year
• ARC-Lab-UF / sv-tutorial
  SystemVerilog Tutorial
  ☆166Updated 3 months ago
• raulbehl / 100DaysOfRTL
  100 Days of RTL
  ☆390Updated last year
• ItzzInfinity / 100-days-of-RTL
  Trying to get a new skill
  ☆25Updated 8 months ago
• maazm007 / vsdsquadron-mini-internship
  VSDSquadron Research Internship 2024 program where we learn about RISC-V processor and VLSI Design using various open source tools.
  ☆30Updated last month
• arm-university / VLSI-Fundamentals-Education-Kit
  Gain an understanding of the fundamentals of Very Large-Scale Integration (VLSI), including how the theories and concepts can be applied …
  ☆265Updated 3 months ago
• asinghani / open-eda-course
  Curriculum for a university course to teach chip design using open source EDA tools
  ☆107Updated last year
• FPGADude / Digital-Design
  Verilog HDL files
  ☆149Updated last year
• Ummidichandrika / 100-Days-of-RTL
  ☆115Updated last year
• AngeloJacobo / OpenLANE-Sky130-Physical-Design-Workshop
  Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130
  ☆65Updated 2 years ago
• iammituraj / pequeno_riscv
  Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.
  ☆112Updated last week
• SRA-VJTI / synapse32
  An inhouse RISC-V 32-bits CPU
  ☆16Updated 2 months ago
• raysalemi / Python4RTLVerification
  ☆164Updated 2 years ago
• hdl-modules / hdl-modules
  A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
  ☆178Updated 2 weeks ago
• Akash-Perla / ASIC-Design
  This repository contains the tasks performed for VL508- Physical Design of ASIC Course (Fall 2024)
  ☆13Updated 9 months ago
• ShonTaware / OpenSource_Physical_Design
  This repository contains all the contents studied and created during the Advanced Physical Design Workshop using OpenLANE and SKY130 PDK
  ☆42Updated 3 years ago
• bmurmann / EE628
  EE 628: Analysis and Design of Integrated Circuits (University of Hawaiʻi at Mānoa)
  ☆164Updated 3 weeks ago
• abdelazeem201 / ASIC-Design-Roadmap
  The journey of designing an ASIC (application specific integrated circuit) is long and involves a number of major steps – moving from a c…
  ☆386Updated last month
• arm-university / Introduction-to-SoC-Design-Education-Kit
  Gain an introductory knowledge to the basics of SoC design and key skills required to implement a simple SoC on an FPGA, and write embedd…
  ☆139Updated 3 months ago
• mikeroyal / Verilog-SystemVerilog-Guide
  Verilog/SystemVerilog Guide
  ☆72Updated last year
• abdelazeem201 / Cadence-RTL-to-GDSII-Flow
  In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.
  ☆75Updated last year
• D-curs-D / Inverter-design-and-analysis-using-sky130pdk
  Design and Analysis of CMOS Inverter using the sky130 pdk and various open source tools
  ☆115Updated 3 years ago
• fayizferosh / soc-design-and-planning-nasscom-vsd
  2 Week digital VLSI SoC design and planning workshop with complete RTL2GDSII flow organised by VSD in collaboration with NASSCOM (Advance…
  ☆26Updated last year
• michaelehab / AES-Verilog
  Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL
  ☆110Updated 3 years ago
• snbk001 / Verilog-Design-Examples
  Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy mach…
  ☆152Updated last year
• TL-X-org / TL-V_Projects
  An overview of TL-Verilog resources and projects
  ☆81Updated 5 months ago
• brabect1 / sta_basics_course
  Introductory course into static timing analysis (STA).
  ☆97Updated last month
• MahmouodMagdi / Clock-Domain-Crossing-Synchronizers
  Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…
  ☆63Updated last year
• ekb0412 / 100DaysofRTL
  "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado
  ☆93Updated 2 years ago