mvcisback / py-aigerLinks
py-aiger: A python library for manipulating sequential and combinatorial circuits encoded using `and` & `inverter` gates (AIGs).
☆47Updated 8 months ago
Alternatives and similar repositories for py-aiger
Users that are interested in py-aiger are comparing it to the libraries listed below
Sorting:
- Python version of tools to work with AIG formatted files☆12Updated 3 months ago
- AMulet 2. - A better AIG Multiplier Examination Tool☆25Updated 2 years ago
- AIGER And-Inverter-Graph Library☆86Updated 3 weeks ago
- ☆12Updated 2 years ago
- Random Generator of Btor2 Files☆10Updated last year
- Reads a state transition system and performs property checking☆85Updated 6 months ago
- Collection for submission (Hardware Model Checking Benchmark)☆10Updated 10 months ago
- A generic parser and tool package for the BTOR2 format.☆41Updated 3 months ago
- ☆17Updated 4 years ago
- E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)☆35Updated last year
- ☆22Updated 2 months ago
- Hardware Formal Verification Tool☆62Updated last week
- ANSI-C benchmarks generated from Verilog RTL circuits with safety assertions. Used for Formal Property Verification.☆15Updated 6 years ago
- MapTune: Advancing ASIC Technology Mapping via Reinforcement Learning Guided Library Tuning Mingju Liu, Daniel Robinson, Yingjie Li, Cunx…☆21Updated 4 months ago
- SATZilla SAT feature extraction tool☆10Updated last year
- Logic Synthesis System from UC Berkeley (Unofficial Distribution)☆15Updated 6 years ago
- This is an official implementation for "DeepGate: Learning Neural Representations of Logic Gates".☆23Updated 2 years ago
- A high-efficiency hybrid solving CEC algorithm☆13Updated 2 years ago
- rIC3 model checker for Hardware Model Checking Competition 2024(HWMCC'24) submission☆12Updated last month
- CoreIR Symbolic Analyzer☆73Updated 4 years ago
- ☆13Updated 4 years ago
- An advanced circuit-based sat solver☆29Updated 6 months ago
- Arithmetic multiplier benchmarks☆11Updated 7 years ago
- ☆14Updated 7 years ago
- LLM Evaluation Benchmark on Hardware Formal Verification☆28Updated 4 months ago
- Binary Decision Diagrams (BDDs) in pure Python and Cython wrappers of CUDD, Sylvan, and BuDDy☆203Updated last week
- Integer Multiplier Generator for Verilog☆23Updated last month
- Research paper based on or related to ABC.☆51Updated last month
- C++ implementation of FRAIGs. Won the 1st place in 2018 Cadence-sponsored contest in NTU DSnP.☆10Updated 4 years ago
- ☆10Updated 3 years ago