mvcisback / py-aigerLinks
py-aiger: A python library for manipulating sequential and combinatorial circuits encoded using `and` & `inverter` gates (AIGs).
☆49Updated last month
Alternatives and similar repositories for py-aiger
Users that are interested in py-aiger are comparing it to the libraries listed below
Sorting:
- Python version of tools to work with AIG formatted files☆12Updated 8 months ago
- ☆13Updated 3 years ago
- Random Generator of Btor2 Files☆10Updated 2 years ago
- AMulet 2. - A better AIG Multiplier Examination Tool☆26Updated last month
- E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)☆41Updated last year
- ☆14Updated 8 years ago
- SATZilla SAT feature extraction tool☆11Updated 3 weeks ago
- A framework to ease parallelization of sequential SAT solvers☆30Updated 3 weeks ago
- rIC3 model checker for Hardware Model Checking Competition 2024(HWMCC'24) submission☆11Updated 7 months ago
- MapTune: Advancing ASIC Technology Mapping via Reinforcement Learning Guided Library Tuning Mingju Liu, Daniel Robinson, Yingjie Li, Cunx…☆22Updated 10 months ago
- SMTSampler: Efficient Stimulus Generation from Complex SMT Constraints☆31Updated 6 years ago
- AIGER And-Inverter-Graph Library☆97Updated last month
- ☆10Updated 4 years ago
- Arithmetic multiplier benchmarks☆12Updated 8 years ago
- Reads a state transition system and performs property checking☆90Updated 5 months ago
- Awesome machine learning for logic synthesis☆30Updated 3 years ago
- C++ implementation of FRAIGs. Won the 1st place in 2018 Cadence-sponsored contest in NTU DSnP.☆10Updated 5 years ago
- A fork of the Kissat SAT solver with additional features. Supports incremental solving.☆17Updated 3 years ago
- Logic Synthesis System from UC Berkeley (Unofficial Distribution)☆15Updated 6 years ago
- ☆19Updated 5 years ago
- ☆13Updated 5 years ago
- CoreIR Symbolic Analyzer☆74Updated 5 years ago
- GuidedSampler: Coverage-guided Sampling of SMT Solutions☆15Updated 7 months ago
- Control Logic Synthesis: Drawing the Rest of the OWL☆13Updated last year
- An advanced circuit-based sat solver☆36Updated 11 months ago
- BTOR2 MLIR project☆26Updated 2 years ago
- Collection for submission (Hardware Model Checking Benchmark)☆13Updated 3 months ago
- A generic parser and tool package for the BTOR2 format.☆46Updated 4 months ago
- This is an official implementation for "DeepGate: Learning Neural Representations of Logic Gates".☆24Updated 2 years ago
- QuteRTL: A RTL Front-End Towards Intelligent Synthesis and Verification☆16Updated 9 years ago