antmicro / renode-linux-runner-action
Run your tests in a configurable, emulated Linux environment with a custom kernel and access to virtual peripherals
☆11Updated 9 months ago
Related projects ⓘ
Alternatives and complementary repositories for renode-linux-runner-action
- This repository contains sample code integrating Renode with Verilator☆17Updated 2 weeks ago
- ☆18Updated 9 months ago
- ☆12Updated 2 months ago
- 🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.☆29Updated 2 years ago
- A simple Python utility for extracting documentation snippets from tutorials.☆13Updated last year
- Raw image/video data analyzer☆44Updated this week
- datasheet generator☆28Updated 4 months ago
- Open Source FPGA toolchain and documentation for QuickLogic devices and eFPGA IP☆36Updated 3 years ago
- Bare metal example software projects for PolarFire SoC☆27Updated 5 months ago
- GitHub Action allowing to run tests in the Renode framework☆16Updated last month
- A sphinx extension that allows including wavedrom diagrams by using its text-based representation☆35Updated 2 months ago
- lbuild: a generic, modular code generator in Python 3☆37Updated last year
- Icestudio collection for standard Input-Output in different devices☆14Updated 4 months ago
- Nix flake for openXC7☆27Updated this week
- Simulate any equipment (multimeter, oscilloscope, detectors, motors) over tcp, udp or serial line☆27Updated last year
- A usable language reference for VHDL that is concise, direct, and easy to understand.☆25Updated last year
- Small footprint and configurable Inter-Chip communication cores☆54Updated last month
- Auto place components into pcbnew from a centroid file. Useful for maintaining a common board form factor.☆23Updated 2 months ago
- ☆13Updated 2 months ago
- Adapter board exposing SATA M.2 SSD on FMC board-to-board connector☆11Updated last year
- Sphinx Extension which generates various types of diagrams from Verilog code.☆55Updated last year
- An open source replacement of the Xilinx bootgen application.☆99Updated 8 months ago
- An abstract language model of VHDL written in Python.☆50Updated last week
- Hardware Design Tool - Mixed Signal Simulation with Verilog☆70Updated 5 years ago
- Open Hardware carrier board supporting modules with Zynq 7000 All Programmable SoC devices.☆53Updated last year
- Filter builder tool☆17Updated 2 years ago
- ☆12Updated 4 months ago
- UserspaceIO helper library☆30Updated 8 months ago
- OSVVM project simulation scripts. Scripts are tedious. These scripts simplify the steps to compile your project for simulation☆10Updated last week
- EVEREST: e-Versatile Research Stick for peoples☆35Updated last year