antmicro / warp-pipe
☆13Updated 2 months ago
Related projects ⓘ
Alternatives and complementary repositories for warp-pipe
- Small footprint and configurable SPI core☆39Updated 2 weeks ago
- Virtual development board for HDL design☆39Updated last year
- Small footprint and configurable Inter-Chip communication cores☆54Updated last month
- FPGA board-level debugging and reverse-engineering tool☆29Updated last year
- Mirror of https://codeberg.org/ECP5-PCIe/ECP5-PCIe☆92Updated last year
- cocotb extension for nMigen☆15Updated 2 years ago
- RISC-V Processor written in Amaranth HDL☆33Updated 2 years ago
- Siglent SDS1x0xX-E FPGA bitstreams☆40Updated last year
- Small footprint and configurable JESD204B core☆40Updated last month
- a noodly Amaranth HDL-wrapper for FPGA SerDes' presenting a PIPE PHY interface☆31Updated 2 years ago
- ☆22Updated 2 years ago
- assorted library of utility cores for amaranth HDL☆81Updated 2 months ago
- Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores☆50Updated last year
- Flip flop setup, hold & metastability explorer tool☆31Updated 2 years ago
- ☆43Updated 7 months ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆23Updated last week
- Python script to transform a VCD file to wavedrom format☆74Updated 2 years ago
- Bitstream relocation and manipulation tool.☆40Updated last year
- USB virtual model in C++ for Verilog☆28Updated last month
- sample VCD files☆36Updated 9 months ago
- ☆29Updated 3 years ago
- A configurable USB 2.0 device core☆30Updated 4 years ago
- Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards☆42Updated this week
- A demonstration showing how several components can be compsed to build a simulated spectrogram☆40Updated 7 months ago
- An example project which uses many of the ideas and features of the hVHDL libraries like fixed and floating point math modules and has bu…☆24Updated 4 months ago
- 📊 Tools collection (NumPy + Matplotlib based) to do spectral analysis and calculate the key performance parameters of an ADC☆19Updated last year
- A padring generator for ASICs☆22Updated last year
- ☆39Updated last year
- Dockerized FPGA toolchain experiments☆28Updated 9 months ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆60Updated 3 weeks ago