antmicro / warp-pipeLinks
☆16Updated last year
Alternatives and similar repositories for warp-pipe
Users that are interested in warp-pipe are comparing it to the libraries listed below
Sorting:
- Mirror of https://codeberg.org/ECP5-PCIe/ECP5-PCIe☆102Updated 2 years ago
- Small footprint and configurable Inter-Chip communication cores☆66Updated 3 weeks ago
- FPGA board-level debugging and reverse-engineering tool☆38Updated 2 years ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆38Updated last week
- PCIe analyzer experiments☆63Updated 5 years ago
- Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.☆80Updated 3 years ago
- Python script to transform a VCD file to wavedrom format☆81Updated 3 years ago
- Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores☆52Updated 2 years ago
- Generate Zynq configurations without using the vendor GUI☆30Updated 2 years ago
- Open Source AES☆31Updated last month
- Bitstream relocation and manipulation tool.☆48Updated 2 years ago
- Small footprint and configurable SPI core☆46Updated 3 weeks ago
- Bitfiltrator: A general approach for reverse-engineering Xilinx bitstream formats☆46Updated 2 years ago
- Virtual development board for HDL design☆42Updated 2 years ago
- assorted library of utility cores for amaranth HDL☆97Updated last year
- RISC-V Processor written in Amaranth HDL☆39Updated 3 years ago
- ☆34Updated 4 years ago
- ☆32Updated 2 years ago
- FTDI FT600 SuperSpeed USB3.0 to AXI bus master☆94Updated 5 years ago
- Extensible FPGA control platform☆61Updated 2 years ago
- Small footprint and configurable JESD204B core☆49Updated 3 weeks ago
- 🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.☆31Updated 3 years ago
- LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled☆66Updated this week
- LiteX development baseboards arround the SQRL Acorn.☆71Updated 7 months ago
- Scripts to build and use docker images including GHDL☆43Updated 11 months ago
- Xilinx virtual cable server for generic FTDI 4232H.☆59Updated last year
- BrightAI B.V. open sources its Blackwire RTL FPGA smartNIC implementation of WireGuard☆59Updated 2 years ago
- Experimental flows using nextpnr for Xilinx devices☆51Updated 5 months ago
- cocotb extension for nMigen☆17Updated 3 years ago
- ☆14Updated 2 years ago