Alternatives and similar repositories for warp-pipe:

Users that are interested in warp-pipe are comparing it to the libraries listed below

• dbhi / vboard
  Virtual development board for HDL design
  ☆41Updated 2 years ago
• enjoy-digital / liteiclink
  Small footprint and configurable Inter-Chip communication cores
  ☆57Updated last month
• antmicro / topwrap
  A Python package for generating HDL wrappers and top modules for HDL sources
  ☆32Updated last month
• litex-hub / litespi
  Small footprint and configurable SPI core
  ☆41Updated 3 months ago
• ECP5-PCIe / ECP5-PCIe
  Mirror of https://codeberg.org/ECP5-PCIe/ECP5-PCIe
  ☆95Updated last year
• greatscottgadgets / bucatini
  a noodly Amaranth HDL-wrapper for FPGA SerDes' presenting a PIPE PHY interface
  ☆32Updated 3 years ago
• mattvenn / flipflop_demo
  Flip flop setup, hold & metastability explorer tool
  ☆34Updated 2 years ago
• wyvernSemi / usbModel
  USB virtual model in C++ for Verilog
  ☆29Updated 6 months ago
• GuzTech / misato
  RISC-V Processor written in Amaranth HDL
  ☆37Updated 3 years ago
• craigjb / fuse-zynq
  Generate Zynq configurations without using the vendor GUI
  ☆30Updated last year
• mattvenn / gtkwave-python-filter-process
  ☆33Updated 4 years ago
• hdlguy / make_for_vivado
  experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.
  ☆22Updated last year
• sparrowgrine / prjtritium
  ☆22Updated 3 years ago
• blackmesalabs / sump3
  sump3 logic analyzer
  ☆19Updated 4 months ago
• lambdaconcept / lambdasoc
  ☆44Updated last month
• lambdaconcept / lambdaUSB
  A configurable USB 2.0 device core
  ☆31Updated 4 years ago
• ZipCPU / fftdemo
  A demonstration showing how several components can be compsed to build a simulated spectrogram
  ☆42Updated last year
• enjoy-digital / litejesd204b
  Small footprint and configurable JESD204B core
  ☆42Updated 3 months ago
• amaranth-farm / amlib
  assorted library of utility cores for amaranth HDL
  ☆87Updated 7 months ago
• tmeissner / cryptocores
  cryptography ip-cores in vhdl / verilog
  ☆40Updated 4 years ago
• alexforencich / pin-uart
  FPGA board-level debugging and reverse-engineering tool
  ☆36Updated 2 years ago
• antmicro / usb-test-suite-build
  Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores
  ☆50Updated last year
• openXC7 / xc7k325t-blinky-nextpnr
  ☆45Updated 2 years ago
• 360nosc0pe / scope
  Siglent SDS1x0xX-E FPGA bitstreams
  ☆41Updated 3 months ago
• antmicro / embench-tester
  ☆13Updated last year
• hdl / constraints
  Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards
  ☆44Updated this week
• kbob / nmigen-examples
  I want to learn [n]Migen.
  ☆40Updated 5 years ago
• openXC7 / nextpnr-xilinx
  Experimental flows using nextpnr for Xilinx devices
  ☆42Updated last month
• ekiwi / icesugar-chisel
  Chisel Examples for the iCESugar FPGA Board
  ☆11Updated 3 years ago
• stevenbell / csirx
  Open-source CSI-2 receiver for Xilinx UltraScale parts
  ☆37Updated 5 years ago