antmicro / warp-pipeLinks
☆16Updated last year
Alternatives and similar repositories for warp-pipe
Users that are interested in warp-pipe are comparing it to the libraries listed below
Sorting:
- Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.☆81Updated 3 years ago
- Mirror of https://codeberg.org/ECP5-PCIe/ECP5-PCIe☆102Updated 2 years ago
- Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores☆52Updated 2 years ago
- FPGA board-level debugging and reverse-engineering tool☆38Updated 2 years ago
- assorted library of utility cores for amaranth HDL☆99Updated last year
- Small footprint and configurable JESD204B core☆50Updated 2 months ago
- Small footprint and configurable SPI core☆46Updated 2 weeks ago
- Bitstream relocation and manipulation tool.☆50Updated 3 years ago
- PCIe analyzer experiments☆63Updated 5 years ago
- FTDI FT600 SuperSpeed USB3.0 to AXI bus master☆97Updated 5 years ago
- VCD viewer☆98Updated 3 months ago
- 🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.☆31Updated 3 years ago
- ☆26Updated 2 years ago
- ☆33Updated 3 years ago
- Bitfiltrator: A general approach for reverse-engineering Xilinx bitstream formats☆48Updated 2 years ago
- ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…☆63Updated 3 weeks ago
- Python script to transform a VCD file to wavedrom format☆82Updated 3 years ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆69Updated last week
- Small footprint and configurable Inter-Chip communication cores☆66Updated 2 months ago
- 📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.☆86Updated last week
- Virtual development board for HDL design☆42Updated 2 years ago
- ☆88Updated 2 months ago
- ☆34Updated 4 years ago
- Generate address space documentation HTML from compiled SystemRDL input☆59Updated last month
- Basic loadout for SQRL Acorn CLE 215/215+ board. Blinks all LEDs, outputs square waves on all 12 GPIO outputs☆69Updated 4 years ago
- LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled☆100Updated this week
- Open Source AES☆31Updated 2 months ago
- The first-ever opensource RTL core for PCIE EndPoint. Without vendor-locked HMs for Data Link, Transaction, Application layers; With stan…☆52Updated last week
- FuseSoC standard core library☆151Updated 3 weeks ago
- Spen's Official OpenOCD Mirror☆51Updated 9 months ago