antmicro / kenning-pipeline-manager
☆17Updated last month
Related projects ⓘ
Alternatives and complementary repositories for kenning-pipeline-manager
- A Python package for generating HDL wrappers and top modules for HDL sources☆23Updated last week
- Virtual development board for HDL design☆39Updated last year
- The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …☆47Updated this week
- A padring generator for ASICs☆22Updated last year
- Drawio => VHDL and Verilog☆51Updated last year
- RISC-V Processor written in Amaranth HDL☆31Updated 2 years ago
- Generate Zynq configurations without using the vendor GUI☆30Updated last year
- sump3 logic analyzer☆16Updated 7 months ago
- ☆32Updated last year
- A pipelined RISC-V processor☆47Updated 11 months ago
- Verilog Modules and Python Scripts for Creating IP Core Build Directories☆29Updated last year
- SAR ADC on tiny tapeout☆34Updated this week
- USB virtual model in C++ for Verilog☆28Updated 3 weeks ago
- Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards☆42Updated this week
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆72Updated 2 months ago
- experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.☆22Updated 10 months ago
- Framework Open EDA Gui☆60Updated this week
- FPGA examples on Google Colab☆17Updated 7 months ago
- A current mode buck converter on the SKY130 PDK☆26Updated 3 years ago
- Solving Sudokus using open source formal verification tools☆15Updated 2 years ago
- LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled☆53Updated this week
- ☆57Updated 3 years ago
- ☆18Updated this week
- Provides automation scripts for building BFMs☆16Updated 2 years ago
- 📊 Tools collection (NumPy + Matplotlib based) to do spectral analysis and calculate the key performance parameters of an ADC☆19Updated last year
- ☆12Updated 2 months ago
- Proposed RISC-V Composable Custom Extensions Specification☆67Updated 6 months ago
- Python script to transform a VCD file to wavedrom format☆73Updated 2 years ago
- Open source process design kit for 28nm open process