kuznia-rdzeni / coreblocksLinks
RISC-V out-of-order core for education and research purposes
☆62Updated last week
Alternatives and similar repositories for coreblocks
Users that are interested in coreblocks are comparing it to the libraries listed below
Sorting:
- System on Chip toolkit for Amaranth HDL☆92Updated 11 months ago
- End-to-end synthesis and P&R toolchain☆87Updated 3 weeks ago
- User-friendly explanation of Yosys options☆113Updated 3 years ago
- A replacement for gtkwave, written in Rust with high-performance and larger-than-memory traces in mind.☆19Updated 3 years ago
- RISC-V Processor written in Amaranth HDL☆39Updated 3 years ago
- Exploring gate level simulation☆58Updated 4 months ago
- A configurable and approachable tool for FPGA debugging and rapid prototyping.☆140Updated 5 months ago
- A Rust VCD parser intended to be the backend of a Waveform Viewer(built using egui) that supports dynamically loaded rust plugins.☆48Updated 8 months ago
- Another size-optimized RISC-V CPU for your consideration.☆58Updated last week
- An FPGA reverse engineering and documentation project☆54Updated this week
- Industry standard I/O for Amaranth HDL☆29Updated 11 months ago
- VS Code based debugger for hardware designs in Amaranth or Verilog☆39Updated 9 months ago
- RISC-V CPU implementation in Amaranth HDL (aka nMigen)☆32Updated last year
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆106Updated 2 weeks ago
- Logic circuit analysis and optimization☆42Updated 3 weeks ago
- Greyhound on IHP SG13G2 0.13 μm BiCMOS process☆56Updated last week
- PicoRV☆44Updated 5 years ago
- CoreScore☆163Updated last month
- Nix flake for openXC7☆41Updated 5 months ago
- Dual-issue RV64IM processor for fun & learning☆64Updated 2 years ago
- Documenting Lattice's 28nm FPGA parts☆144Updated last year
- RFCs for changes to the Amaranth language and standard components☆18Updated last month
- Hot Reconfiguration Technology demo☆40Updated 3 years ago
- Board definitions for Amaranth HDL☆118Updated 3 weeks ago
- An automatic clock gating utility☆50Updated 5 months ago
- ☆70Updated last year
- wellen: waveform datastructures in Rust. Fast VCD, FST and GHW parsing for waveform viewers.☆86Updated 3 weeks ago
- Experiments with Yosys cxxrtl backend☆49Updated 8 months ago
- Gate-level visualization generator for SKY130-based chip designs.☆21Updated 4 years ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆118Updated 2 years ago