kuznia-rdzeni / coreblocksLinks
RISC-V out-of-order core for education and research purposes
☆81Updated last week
Alternatives and similar repositories for coreblocks
Users that are interested in coreblocks are comparing it to the libraries listed below
Sorting:
- User-friendly explanation of Yosys options☆113Updated 4 years ago
- End-to-end synthesis and P&R toolchain☆94Updated last month
- System on Chip toolkit for Amaranth HDL☆98Updated last year
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆111Updated last month
- Exploring gate level simulation☆59Updated 9 months ago
- Dual-issue RV64IM processor for fun & learning☆64Updated 2 years ago
- RISC-V Processor written in Amaranth HDL☆39Updated 4 years ago
- CoreScore☆171Updated 2 months ago
- A replacement for gtkwave, written in Rust with high-performance and larger-than-memory traces in mind.☆19Updated 3 years ago
- PicoRV☆43Updated 5 years ago
- Naive Educational RISC V processor☆94Updated 3 months ago
- A configurable and approachable tool for FPGA debugging and rapid prototyping.☆146Updated last week
- The Critical Path - a rambly FPGA blog☆51Updated 5 years ago
- An FPGA reverse engineering and documentation project☆64Updated this week
- Greyhound on IHP SG13G2 0.13 μm BiCMOS process☆77Updated last month
- Experimental flows using nextpnr for Xilinx devices☆54Updated 2 months ago
- Experimental flows using nextpnr for Xilinx devices☆253Updated last year
- A Rust VCD parser intended to be the backend of a Waveform Viewer(built using egui) that supports dynamically loaded rust plugins.☆49Updated last year
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆120Updated 2 years ago
- PCIe Endpoint on Xilinx 7-Series FPGAs with the PCIE_2_1 hard block and GTP transceivers☆67Updated 9 months ago
- Another size-optimized RISC-V CPU for your consideration.☆58Updated 3 weeks ago
- Project X-Ray Database: XC7 Series☆74Updated 4 years ago
- Gate-level visualization generator for SKY130-based chip designs.☆21Updated 4 years ago
- Mirror of https://codeberg.org/ECP5-PCIe/ECP5-PCIe☆102Updated 2 years ago
- Building and deploying container images for open source electronic design automation (EDA)☆119Updated last year
- ☆22Updated 3 years ago
- ☆89Updated 3 months ago
- Board definitions for Amaranth HDL☆122Updated 4 months ago
- VS Code based debugger for hardware designs in Amaranth or Verilog☆39Updated last year
- ☆72Updated last year