PrincetonUniversity / DuetLinks
☆14Updated 2 years ago
Alternatives and similar repositories for Duet
Users that are interested in Duet are comparing it to the libraries listed below
Sorting:
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆43Updated 3 months ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆112Updated 2 years ago
- A GPU acceleration flow for RTL simulation with batch stimulus☆113Updated last year
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆68Updated last year
- NOCulator is a network-on-chip simulator providing cycle-accurate performance models for a wide variety of networks (mesh, torus, ring, h…☆27Updated 2 years ago
- ☆79Updated this week
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 4 years ago
- ☆61Updated this week
- A unified simulation platform that combines hardware and software, enabling pre-silicon, full-stack, closed-loop evaluation of your robot…☆44Updated 6 months ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 3 months ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆57Updated 3 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆54Updated 5 years ago
- ☆87Updated last year
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆29Updated 2 years ago
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆39Updated 6 years ago
- ☆58Updated 2 years ago
- Next generation CGRA generator☆114Updated last week
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆127Updated 2 years ago
- RISC-V SST CPU Component☆24Updated 3 weeks ago
- Papers, Posters, Presentations, Documentation...☆19Updated last year
- For contributions of Chisel IP to the chisel community.☆66Updated 11 months ago
- CGRA framework with vectorization support.☆35Updated this week
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆88Updated last year
- DASS HLS Compiler☆29Updated 2 years ago
- A simple MIPS-like CPU demo in C++ for Xilinx Vivado HLS☆18Updated 6 years ago
- Tests for example Rocket Custom Coprocessors☆75Updated 5 years ago
- The Task Parallel System Composer (TaPaSCo)☆110Updated 5 months ago
- PDPU: An Open-Source Posit Dot-Product Unit for Deep Learning Applications☆42Updated 2 years ago
- Open source RTL simulation acceleration on commodity hardware☆30Updated 2 years ago
- ☆80Updated last year