PrincetonUniversity / DuetLinks
☆15Updated 2 years ago
Alternatives and similar repositories for Duet
Users that are interested in Duet are comparing it to the libraries listed below
Sorting:
- A GPU acceleration flow for RTL simulation with batch stimulus☆112Updated last year
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆41Updated last month
- ☆86Updated last year
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 3 years ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆28Updated last year
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆54Updated 5 years ago
- Next generation CGRA generator☆112Updated last week
- DASS HLS Compiler☆29Updated last year
- Proposed RISC-V Composable Custom Extensions Specification☆71Updated 2 weeks ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆57Updated 3 years ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆110Updated last year
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆126Updated 2 years ago
- ☆68Updated last week
- The OpenPiton Platform☆29Updated 2 years ago
- A polyhedral compiler for hardware accelerators☆59Updated 11 months ago
- Project repo for the POSH on-chip network generator☆48Updated 3 months ago
- CGRA framework with vectorization support.☆32Updated this week
- ☆58Updated last year
- Runtime-First FPGA Interchange Routing Contest @ FPGA’24☆33Updated last month
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆39Updated 6 years ago
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆73Updated last week
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆82Updated 9 months ago
- Tests for example Rocket Custom Coprocessors☆74Updated 5 years ago
- CIRCT-based HLS compilation flows, debugging, and cosimulation tools.☆49Updated last year
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆69Updated last year
- Open source RTL simulation acceleration on commodity hardware☆28Updated 2 years ago
- Public release☆53Updated 5 years ago
- ☆59Updated this week
- ☆36Updated 4 years ago
- Cluster-level matrix unit integration into GPUs, implemented in Chipyard SoC☆35Updated last month