PrincetonUniversity / Duet
☆15Updated 2 years ago
Alternatives and similar repositories for Duet:
Users that are interested in Duet are comparing it to the libraries listed below
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆28Updated last year
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆38Updated 3 months ago
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆38Updated 6 years ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆101Updated last year
- ☆15Updated 4 years ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 3 years ago
- ☆20Updated last year
- ☆57Updated last year
- ☆87Updated last year
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆52Updated 5 years ago
- CGRA framework with vectorization support.☆27Updated last week
- A GPU acceleration flow for RTL simulation with batch stimulus☆102Updated 11 months ago
- DASS HLS Compiler☆29Updated last year
- A Rocket-based RISC-V superscalar in-order core☆30Updated this week
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆62Updated last year
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆63Updated this week
- ☆49Updated this week
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆81Updated 5 months ago
- Heterogeneous simulator for DECADES Project☆32Updated 9 months ago
- Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…☆62Updated 8 months ago
- Tests for example Rocket Custom Coprocessors☆72Updated 5 years ago
- For contributions of Chisel IP to the chisel community.☆59Updated 4 months ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆50Updated 3 years ago
- Next generation CGRA generator☆109Updated this week
- ordspecsim: The Swarm architecture simulator☆24Updated 2 years ago
- The OpenPiton Platform☆28Updated last year
- An Open-Hardware CGRA for accelerated computation on the edge.☆21Updated 6 months ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 10 months ago
- A simple MIPS-like CPU demo in C++ for Xilinx Vivado HLS☆18Updated 5 years ago
- HLS for Networks-on-Chip☆33Updated 4 years ago