Alternatives and similar repositories for eth10g:

Users that are interested in eth10g are comparing it to the libraries listed below

• AngeloJacobo / UberDDR3
  Opensource DDR3 Controller
  ☆319Updated 2 weeks ago
• fusesoc / blinky
  Example LED blinking project for your FPGA dev board of choice
  ☆175Updated 2 months ago
• efabless / raven-picorv32
  Silicon-validated SoC implementation of the PicoSoc/PicoRV32
  ☆265Updated 4 years ago
• ZipCPU / wbuart32
  A simple, basic, formally verified UART controller
  ☆300Updated last year
• fpganinja / taxi
  AXI, AXI stream, Ethernet, and PCIe components in System Verilog
  ☆199Updated this week
• HDLForBeginners / Examples
  ☆92Updated last year
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆134Updated last month
• enjoy-digital / liteeth
  Small footprint and configurable Ethernet core
  ☆236Updated 2 weeks ago
• antmicro / fastvdma
  Antmicro's fast, vendor-neutral DMA IP in Chisel
  ☆116Updated 5 months ago
• openhwgroup / core-v-cores
  CORE-V Family of RISC-V Cores
  ☆264Updated 2 months ago
• olofk / corescore
  CoreScore
  ☆151Updated 3 months ago
• SpinalHDL / NaxRiscv
  ☆283Updated last month
• enjoy-digital / usb3_pipe
  USB3 PIPE interface for Xilinx 7-Series
  ☆212Updated 3 years ago
• jamieiles / uart
  Verilog UART
  ☆163Updated 11 years ago
• alexforencich / verilog-dsp
  Verilog digital signal processing components
  ☆133Updated 2 years ago
• ulixxe / usb_cdc
  Single/Multi-channel Full Speed USB interface for FPGA and ASIC designs
  ☆167Updated last year
• openhwgroup / cvw
  CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…
  ☆369Updated this week
• ZipCPU / sdspi
  SD-Card controller, using either SPI, SDIO, or eMMC interfaces
  ☆277Updated last week
• SparcLab / OpenSERDES
  Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology.
  ☆155Updated 3 years ago
• f4pga / f4pga-arch-defs
  FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
  ☆282Updated this week
• dineshannayya / riscduino
  Arduino compatible Risc-V Based SOC
  ☆148Updated 9 months ago
• pulp-platform / cheshire
  A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
  ☆255Updated this week
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆96Updated last month
• SpinalHDL / SaxonSoc
  SoC based on VexRiscv and ICE40 UP5K
  ☆157Updated last month
• ZipCPU / autofpga
  A utility for Composing FPGA designs from Peripherals
  ☆178Updated 4 months ago
• hamsternz / DisplayPort_Verilog
  A Verilog implementation of DisplayPort protocol for FPGAs
  ☆247Updated 6 years ago
• pulp-platform / mempool
  A 256-RISC-V-core system with low-latency access into shared L1 memory.
  ☆290Updated this week
• enjoy-digital / litedram
  Small footprint and configurable DRAM core
  ☆410Updated last week
• stnolting / neorv32-verilog
  ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
  ☆81Updated this week
• zeroasiccorp / switchboard
  Communication framework for RTL simulation and emulation.
  ☆284Updated last month