10Gb Ethernet Switch
☆277Sep 17, 2026Updated 3 weeks ago
Alternatives and similar repositories for eth10g
Users that are interested in eth10g are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Wishbone SATA Controller☆28Sep 17, 2026Updated 3 weeks ago
- Verilog Ethernet Switch (layer 2)☆60Oct 18, 2023Updated 2 years ago
- Opensource DDR3 Controller☆485Sep 12, 2026Updated 3 weeks ago
- LiteX based White Rabbit PCIe NIC developped for Warsaw University of Technology.☆27Sep 23, 2026Updated 2 weeks ago
- Open source FPGA-based NIC and platform for in-network compute☆2,488Jul 5, 2024Updated 2 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- USB -> AXI Debug Bridge☆47Jun 5, 2021Updated 5 years ago
- RTL implementation of the ethernet physical layer PCS for 10GBASE-R and 40GBASE-R.☆39Jan 2, 2024Updated 2 years ago
- Verilog Ethernet components for FPGA implementation☆3,119Feb 27, 2025Updated last year
- Userspace DMA library for Zynq-based SoCs☆16Jan 22, 2019Updated 7 years ago
- Bus bridges and other odds and ends☆706Sep 11, 2026Updated 3 weeks ago
- A collection of demonstration digital filters☆178Jan 18, 2024Updated 2 years ago
- ☆24Feb 15, 2023Updated 3 years ago
- Small footprint and configurable PCIe core☆733Updated this week
- A small, light weight, RISC CPU soft core☆1,590Sep 16, 2026Updated 3 weeks ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- SD-Card controller, using either SPI, SDIO, or eMMC interfaces☆417Aug 10, 2026Updated last month
- RTL implementation of the low latency ethernet modules for the NASDAQ HFT FPGA project.☆71Jan 10, 2024Updated 2 years ago
- Implements a Gaussian Mixture model in JavaScript☆10Dec 3, 2021Updated 4 years ago
- mirror of https://git.elphel.com/Elphel/eddr3☆42Oct 16, 2017Updated 8 years ago
- AXI, AXI stream, Ethernet, and PCIe components in System Verilog☆966Aug 28, 2026Updated last month
- A wishbone controlled scope for FPGA's☆95Jan 12, 2024Updated 2 years ago
- Ethernet switch implementation written in Verilog☆66Jun 13, 2023Updated 3 years ago
- Quite OK image compression Verilog implementation☆24Nov 27, 2024Updated last year
- Verilog PCI express components☆1,669Apr 26, 2024Updated 2 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- ☆43Jul 4, 2026Updated 3 months ago
- An MPEG2 video decoder, written in Verilog and implemented in an FPGA chip.☆27Apr 24, 2019Updated 7 years ago
- 基于Kintex-7 XC7K325T的高性能FPGA功能验证板☆19Feb 13, 2020Updated 6 years ago
- A DDR3 memory controller in Verilog for various FPGAs☆640Oct 10, 2021Updated 4 years ago
- A utility for Composing FPGA designs from Peripherals☆193Aug 31, 2026Updated last month
- ☆37Sep 10, 2026Updated 3 weeks ago
- Computational Storage Device based on the open source project OpenSSD.☆31Oct 25, 2020Updated 5 years ago
- Scalable Network Stack for FPGAs (TCP/IP, RoCEv2)☆969Aug 3, 2026Updated 2 months ago
- MurPhySDR is an open source software-defined radio platform based on the AD9364 transceiver IC.☆14Jul 9, 2024Updated 2 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- 10GbE XGMII TCP/IPv4 packet generator in C, co-simulating with Verilog, SystemVerilog and VHDL☆29Jan 28, 2025Updated last year
- High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model☆35Feb 2, 2026Updated 8 months ago
- 10G Ethernet MAC implementation☆25Jul 13, 2020Updated 6 years ago
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,714Sep 24, 2026Updated 2 weeks ago
- Various HDL (Verilog) IP Cores☆935Jul 1, 2021Updated 5 years ago
- Verilog module to transmit/receive to/from RGMII compatible ethernet PHY☆33Dec 31, 2022Updated 3 years ago
- Open source FPGA-based NIC and platform for in-network compute☆71Aug 21, 2025Updated last year