Alternatives and similar repositories for eth10g:

Users that are interested in eth10g are comparing it to the libraries listed below

• AngeloJacobo / UberDDR3
  Opensource DDR3 Controller
  ☆265Updated this week
• openhwgroup / core-v-mcu
  This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.
  ☆172Updated last year
• alexforencich / verilog-dsp
  Verilog digital signal processing components
  ☆126Updated 2 years ago
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆133Updated last week
• ZipCPU / wbuart32
  A simple, basic, formally verified UART controller
  ☆288Updated last year
• alexforencich / cocotbext-pcie
  PCI express simulation framework for Cocotb
  ☆149Updated last year
• antmicro / fastvdma
  Antmicro's fast, vendor-neutral DMA IP in Chisel
  ☆113Updated 2 months ago
• ZipCPU / sdspi
  SD-Card controller, using either SPI, SDIO, or eMMC interfaces
  ☆240Updated last month
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆126Updated 3 weeks ago
• waviousllc / wav-lpddr-hw
  Wavious DDR (WDDR) Physical interface (PHY) Hardware
  ☆99Updated 3 years ago
• someone755 / ddr3-controller
  A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs
  ☆65Updated 2 years ago
• openhwgroup / core-v-cores
  CORE-V Family of RISC-V Cores
  ☆231Updated last week
• SpinalHDL / NaxRiscv
  ☆275Updated last week
• efabless / raven-picorv32
  Silicon-validated SoC implementation of the PicoSoc/PicoRV32
  ☆264Updated 4 years ago
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆177Updated this week
• openhwgroup / cv32e40x
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆226Updated 3 months ago
• SparcLab / OpenSERDES
  Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology.
  ☆150Updated 2 years ago
• YosysHQ / nerv
  Naive Educational RISC V processor
  ☆78Updated 4 months ago
• ee-uet / UETRV-PCore
  Linux Capable 32-bit RISC-V based SoC in System Verilog
  ☆60Updated 3 months ago
• ataradov / riscv
  Verilog implementation of a RISC-V core
  ☆108Updated 6 years ago
• AUCOHL / DFFRAM
  Standard Cell Library based Memory Compiler using FF/Latch cells
  ☆141Updated 8 months ago
• hamsternz / Rudi-RV32I
  A rudimental RISCV CPU supporting RV32I instructions, in VHDL
  ☆117Updated 4 years ago
• wyvernSemi / pcievhost
  PCIe (1.0a to 2.0) Virtual Root Complex model for Verilog, with Endpoint capabilities
  ☆92Updated 2 weeks ago
• SpinalHDL / VexiiRiscv
  Like VexRiscv, but, Harder, Better, Faster, Stronger
  ☆144Updated this week
• SystemRDL / PeakRDL
  Control and status register code generator toolchain
  ☆112Updated 2 months ago
• hdl-modules / hdl-modules
  A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
  ☆152Updated this week
• ZipCPU / vgasim
  A Video display simulator
  ☆161Updated 7 months ago
• enjoy-digital / litedram
  Small footprint and configurable DRAM core
  ☆390Updated last month
• HDLForBeginners / Examples
  ☆86Updated last year
• freecores / ethmac
  Ethernet MAC 10/100 Mbps
  ☆78Updated 5 years ago