Computational Storage Device based on the open source project OpenSSD.
☆32Oct 25, 2020Updated 6 years ago
Alternatives and similar repositories for nvme_comp_storage
Users that are interested in nvme_comp_storage are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆22Jul 28, 2021Updated 5 years ago
- ☆39Mar 10, 2021Updated 5 years ago
- ☆45Jul 4, 2026Updated 4 months ago
- ☆36Aug 19, 2020Updated 6 years ago
- ☆91Jun 27, 2022Updated 4 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- Cosmos OpenSSD + Hardware and Software source distribution☆264Jul 29, 2022Updated 4 years ago
- Chisel NVMe controller☆29Nov 24, 2022Updated 3 years ago
- NVMe Controller featuring Hardware Acceleration☆123Jun 23, 2021Updated 5 years ago
- An open-source RTL NVMe controller IP for Xilinx FPGA.☆64Feb 25, 2021Updated 5 years ago
- FastPath_MP: An FPGA-based multi-path architecture for direct access from FPGA to NVMe SSD☆38Apr 20, 2021Updated 5 years ago
- Xilinx IP repository☆13May 5, 2018Updated 8 years ago
- It is SATA 3 host controller. Using this you can read write to sata3 sdd/hdd from your fpga logic with simple memory like interface.☆78Jun 2, 2024Updated 2 years ago
- AXI Interface Nand Flash Controller (Sync mode)☆115May 8, 2026Updated 5 months ago
- ChipScope / ILA using XVC (XIlinx Virtual Cable Over PCIe) with a PR (Partial Reconfiguration) design Example.☆15Jun 1, 2017Updated 9 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- ☆21Dec 9, 2018Updated 7 years ago
- Nope☆12Jan 26, 2025Updated last year
- FPGA card looks like an nvme controller, but hides inside pcileech-fpga researching tool.☆42Mar 24, 2025Updated last year
- The official repository of the local FPGA Development Kit.☆22Apr 30, 2019Updated 7 years ago
- This is a multi-core processor specially designed for matrix multiplication using Verilog HDL.☆12Jan 8, 2022Updated 4 years ago
- Open-Channel Open-Way Flash Controller☆26Sep 10, 2021Updated 5 years ago
- A SATA host (HBA) core based on Xilinx FPGA with GTH to read/write hard disk. 一个基于Xilinx FPGA中的GTH的SATA host控制器，用来读写硬盘。☆148Sep 14, 2023Updated 3 years ago
- ☆18Sep 25, 2026Updated last month
- Code for "Baleen: ML Admission & Prefetching for Flash Caches" (FAST 2024).☆28Feb 29, 2024Updated 2 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- User Space NVMe Driver (modified for use on Zynq UltraScale+ MPSoC)☆11Sep 26, 2018Updated 8 years ago
- Example designs for FPGA Drive FMC☆305Oct 26, 2026Updated last week
- include hdlc (miao), 422 grapher, 1553b☆21Oct 10, 2019Updated 7 years ago
- Documentation for the tinyNX33U SoM and related boards☆13Oct 8, 2026Updated 3 weeks ago
- ☆59Sep 30, 2026Updated last month
- 在FPGA上实现SRIO收发控制器☆11Sep 30, 2022Updated 4 years ago
- AXI4-Compatible Verilog Cores, along with some helper modules.☆17Mar 14, 2020Updated 6 years ago
- A scalable RAID system to aggregate performance and capacity of the next-generation storage.☆17Jan 3, 2024Updated 2 years ago
- 标准视频时序生成器☆10Feb 9, 2020Updated 6 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Tightly Coupled Bus, low complexity, high performance system bus.☆13Apr 16, 2026Updated 6 months ago
- ☆15Aug 1, 2023Updated 3 years ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆31Apr 25, 2016Updated 10 years ago
- Implementation of Partially Parellel LDPC Code Decoder in Verilog☆15Jul 23, 2020Updated 6 years ago
- Verilog code that does 2D Low Pass Filter on a greyscale image☆10Sep 22, 2015Updated 11 years ago
- IPv4/UDP stack written in VHDL code, for interfacing with an FPGA over Ethernet☆13Jun 2, 2021Updated 5 years ago
- Verilog IP Cores & Tests☆13May 3, 2018Updated 8 years ago