Alternatives and similar repositories for low-latency-ethernet

Users that are interested in low-latency-ethernet are comparing it to the libraries listed below

• Essenceia / ethernet-physical-layer
  RTL implementation of the ethernet physical layer PCS for 10GBASE-R and 40GBASE-R.
  ☆32Updated 2 years ago
• PremRL / fix-tcpip-project
  Hardware design project of the FIX and TCP/IP offload engines on FPGA, containing HDL codes and Python codes for testing.
  ☆20Updated 2 years ago
• freecores / xge_mac
  Ethernet 10GE MAC
  ☆46Updated 11 years ago
• alexforencich / verilog-cam
  Verilog Content Addressable Memory Module
  ☆115Updated 3 years ago
• shuckc / verilog-utils
  native Verilog pcap, littletoe, bcd, xml and hash modules, with Icarus testbenches
  ☆46Updated 11 years ago
• alexforencich / cocotbext-eth
  Ethernet interface modules for Cocotb
  ☆74Updated 4 months ago
• antmicro / nvme-verilog-pcie
  ☆80Updated 3 years ago
• lewiz-support / LMAC_CORE3
  Ethernet MAC IP Core for 100G/50G/40G/25G/10Gbps
  ☆45Updated 2 years ago
• aquaxis / gemac
  Gigabit MAC + UDP/TCP/IP offload Engine
  ☆35Updated 6 years ago
• hypernyan / eth_vlg
  ☆78Updated 3 years ago
• ultraembedded / core_dbg_bridge
  UART -> AXI Bridge
  ☆69Updated 4 years ago
• FPGA-Networking / Low-Cost-and-Programmable-CRC
  Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"
  ☆43Updated 5 years ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆62Updated last year
• abdelazeem201 / Design-and-ASIC-Implementation-of-32-Point-FFT-Processor
  I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …
  ☆48Updated 2 years ago
• alexforencich / cocotbext-pcie
  PCI express simulation framework for Cocotb
  ☆189Updated 4 months ago
• hpcn-uam / Limago
  Limago: an FPGA-based Open-source 100 GbE TCP/IP Stack
  ☆134Updated 4 years ago
• ishfaqahmed29 / SerDes
  Verilog RTL Design
  ☆46Updated 4 years ago
• sach / System-Verilog-Packet-Library
  System-Veilog Packet Library to configure, randomize, pack/unpack, copy, compare/display different headers
  ☆81Updated 6 years ago
• opensmartnic / cocotb_primer
  understanding of cocotb （In Chinese Only）
  ☆20Updated 7 months ago
• brown9804 / PCIe-Physical-Layer
  Implementation of the PCIe physical layer
  ☆60Updated 6 months ago
• esynr3z / axi_vip_demo
  Xilinx AXI VIP example of use
  ☆43Updated 4 years ago
• alexforencich / verilog-dsp
  Verilog digital signal processing components
  ☆169Updated 3 years ago
• muditbhargava66 / High-Frequency-Trading-FPGA-System
  The High-Frequency Trading FPGA System is an ultra-low latency platform for electronic trading on FPGAs. It features a TCP/IP stack, orde…
  ☆171Updated last year
• adki / DPI_Tutorial
  SystemVerilog Direct Programming Interface (DPI) Tutorial
  ☆76Updated 5 years ago
• mbits-mirafra / SystemVerilogCourse
  This is a detailed SystemVerilog course
  ☆136Updated 10 months ago
• yhqiu16 / NVMeCHA
  NVMe Controller featuring Hardware Acceleration
  ☆101Updated 4 years ago
• learn-cocotb / tutorial
  Complete tutorial code.
  ☆23Updated last year
• ananthbhat94 / DDR4MemoryController
  HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.
  ☆84Updated 7 years ago
• ttchisholm / 10g-low-latency-ethernet
  10G Low Latency Ethernet
  ☆96Updated 2 years ago
• mgtm98 / pcie5_phy
  PCIE 5.0 Graduation project (Verification Team)
  ☆97Updated 2 years ago