RTL implementation of the low latency ethernet modules for the NASDAQ HFT FPGA project.
☆70Jan 10, 2024Updated 2 years ago
Alternatives and similar repositories for low-latency-ethernet
Users that are interested in low-latency-ethernet are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- RTL design for a nasdaq compatible high frequency trading low level. Supports itch on moldudp64.☆115Dec 24, 2023Updated 2 years ago
- FPGA, CuDNN/CUDA & C++ Hybrid infrastructure for ultra low-latency algorithmic trading. Implements market data parsing, order book manage…☆23Apr 24, 2026Updated 4 months ago
- RTL implementation of the ethernet physical layer PCS for 10GBASE-R and 40GBASE-R.☆39Jan 2, 2024Updated 2 years ago
- 10G Low Latency Ethernet☆109Jul 15, 2023Updated 3 years ago
- ☆94Mar 25, 2021Updated 5 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- 📉 fpga-accelerated high-freq trading modules☆32Jan 17, 2026Updated 7 months ago
- Hardware design project of the FIX and TCP/IP offload engines on FPGA, containing HDL codes and Python codes for testing.☆25Dec 11, 2023Updated 2 years ago
- Checksum plays a key role in the TCP/IP headers. In this repo you'll find a efficient FPGA-based solution for a 512-bit AXI4-Stream inter…☆19Aug 28, 2019Updated 7 years ago
- 10GbE XGMII TCP/IPv4 packet generator in C, co-simulating with Verilog, SystemVerilog and VHDL☆29Jan 28, 2025Updated last year
- 10Gb Ethernet Switch☆275Aug 31, 2026Updated last week
- A股订单簿工具,使用逐笔行情进行订单簿重建、千档快照发布、各档委托队列展示等,包括python模型和FPGA HLS实现。☆405Jan 15, 2024Updated 2 years ago
- ☆23Feb 15, 2023Updated 3 years ago
- AXI, AXI stream, Ethernet, and PCIe components in System Verilog