Alternatives and similar repositories for qoiimg

Users that are interested in qoiimg are comparing it to the libraries listed below

• taneroksuz / fpu-sp
  IEEE 754 single precision floating point library in systemverilog and vhdl
  ☆39Updated 3 weeks ago
• ecilasun / NekoIchi
  A simple risc-v CPU /GPU running on an Arty A7-100T FPGA board
  ☆32Updated 4 years ago
• enjoy-digital / liteiclink
  Small footprint and configurable Inter-Chip communication cores
  ☆66Updated 2 weeks ago
• stnolting / neorv32-riscof
  ✔️ Port of RISCOF to check NEORV32 for RISC-V ISA compatibility.
  ☆38Updated last week
• FPGAwars / FLIX-V
  FLIX-V: FPGA, Linux and RISC-V
  ☆42Updated 2 years ago
• olofk / subservient
  Small SERV-based SoC primarily for OpenMPW tapeout
  ☆47Updated last month
• m-labs / VexRiscv-verilog
  Using VexRiscv without installing Scala
  ☆39Updated 4 years ago
• b224hisl / rioschip
  ☆33Updated 3 years ago
• zephray / RISu064
  Dual-issue RV64IM processor for fun & learning
  ☆64Updated 2 years ago
• clairexen / picorv
  PicoRV
  ☆43Updated 5 years ago
• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆55Updated 10 months ago
• FPGA-Research / byteman
  Bitstream relocation and manipulation tool.
  ☆50Updated 3 years ago
• olofk / qerv
  ☆20Updated 8 months ago
• meiniKi / FazyRV
  A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
  ☆110Updated last week
• aignacio / mpsoc_example
  ☆60Updated 4 years ago
• RTimothyEdwards / irsim
  IRSIM switch-level simulator for digital circuits
  ☆35Updated 2 months ago
• siliconcompiler / zerosoc
  Demo SoC for SiliconCompiler.
  ☆62Updated this week
• BrunoLevy / TordBoyau
  A pipelined RISC-V processor
  ☆63Updated 2 years ago
• sylefeb / Silixel
  Exploring gate level simulation
  ☆58Updated 9 months ago
• YosysHQ / nerv
  Naive Educational RISC V processor
  ☆94Updated 3 months ago
• ultraembedded / core_uriscv
  Another tiny RISC-V implementation
  ☆64Updated 4 years ago
• rolandbernard / kleine-riscv
  A small and simple rv32i core written in Verilog
  ☆17Updated 3 years ago
• FelipeFFerreira / ITA-CORES
  RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32
  ☆56Updated 2 years ago
• Wren6991 / libfpga
  Reusable Verilog 2005 components for FPGA designs
  ☆49Updated last month
• Wren6991 / Hazard5
  5-stage RISC-V CPU, originally developed for RISCBoy
  ☆35Updated 2 years ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆127Updated 6 months ago
• CEatBTU / FGPU
  FGPU is a soft GPU-like architecture for FPGAs. It is described in VHDL, fully customizable, and can be programmed using OpenCL.
  ☆64Updated last year
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆111Updated 3 weeks ago
• pulp-platform / RVfplib
  Optimized RISC-V FP emulation for 32-bit processors
  ☆36Updated 4 years ago
• TinyTapeout / tt-gds-action
  Tiny Tapeout GDS Action (using OpenLane)
  ☆15Updated 2 months ago