corundum / ethernet-switch
Ethernet switch implementation written in Verilog
☆44Updated last year
Alternatives and similar repositories for ethernet-switch:
Users that are interested in ethernet-switch are comparing it to the libraries listed below
- Ethernet MAC IP Core for 100G/50G/40G/25G/10Gbps☆41Updated last year
- Open source FPGA-based NIC and platform for in-network compute☆61Updated 4 months ago
- An open-source RTL NVMe controller IP for Xilinx FPGA.☆45Updated 4 years ago
- ☆16Updated 3 years ago
- ☆53Updated 4 years ago
- PCI Express controller model☆48Updated 2 years ago
- ☆53Updated 2 years ago
- Distributed Accelerator OS☆61Updated 2 years ago
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆42Updated 4 years ago
- Verilog Content Addressable Memory Module☆102Updated 3 years ago
- Verilog PCI express components☆21Updated last year
- This repo contains the Limago code☆80Updated 2 years ago
- ☆22Updated 3 years ago
- Ethernet interface modules for Cocotb☆60Updated last year
- Simple hash table on Verilog (SystemVerilog)☆48Updated 8 years ago
- Gigabit MAC + UDP/TCP/IP offload Engine☆31Updated 5 years ago
- corundum work on vu13p☆18Updated last year
- ☆29Updated 2 years ago
- ☆21Updated this week
- Verilog Ethernet components for FPGA implementation☆18Updated last year
- RTL implementation of the ethernet physical layer PCS for 10GBASE-R and 40GBASE-R.☆23Updated last year
- A simple DDR3 memory controller☆54Updated 2 years ago
- understanding of cocotb (In Chinese Only)☆15Updated last year
- Open source 10 Gigabit Ethernet MAC core compatible with Xilinx's non-free 10GMAC☆62Updated 8 years ago
- Checksum plays a key role in the TCP/IP headers. In this repo you'll find a efficient FPGA-based solution for a 512-bit AXI4-Stream inter…☆17Updated 5 years ago
- AMD OpenNIC driver includes the Linux kernel driver☆64Updated 2 months ago
- OPAE porting to Xilinx FPGA devices.☆39Updated 4 years ago
- General Purpose AXI Direct Memory Access☆48Updated 9 months ago
- AXI3 Bus Functional Models (Initiator & Target)☆28Updated 2 years ago
- SystemVerilog DPI "TCP/IP Shunt" (System Verilog/SystemC/Python TCP/IP socket library)☆43Updated 3 weeks ago