corundum / ethernet-switchLinks
Ethernet switch implementation written in Verilog
☆55Updated 2 years ago
Alternatives and similar repositories for ethernet-switch
Users that are interested in ethernet-switch are comparing it to the libraries listed below
Sorting:
- Verilog Content Addressable Memory Module☆113Updated 3 years ago
- Open source FPGA-based NIC and platform for in-network compute☆67Updated 4 months ago
- Verilog PCI express components☆24Updated 2 years ago
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆43Updated 4 years ago
- This repo contains the Limago code☆90Updated 7 months ago
- Distributed Accelerator OS☆63Updated 3 years ago
- ☆34Updated 3 years ago
- ☆16Updated 4 years ago
- AMD OpenNIC driver includes the Linux kernel driver☆70Updated 11 months ago
- Ethernet MAC IP Core for 100G/50G/40G/25G/10Gbps☆46Updated 2 years ago
- ☆70Updated 4 years ago
- ☆80Updated 3 years ago
- Simple hash table on Verilog (SystemVerilog)☆50Updated 9 years ago
- NVMe Controller featuring Hardware Acceleration☆99Updated 4 years ago
- AMD OpenNIC Shell includes the HDL source files☆135Updated 11 months ago
- Example design for the Ethernet FMC using 4 AXI Ethernet Subsystem IP blocks☆72Updated 7 months ago
- Verilog Ethernet components for FPGA implementation☆21Updated 2 years ago
- Ethernet interface modules for Cocotb☆72Updated 3 months ago
- Verilog Ethernet Switch (layer 2)☆50Updated 2 years ago
- TCAM (Ternary Content-Addressable Memory) in Verilog☆54Updated 2 years ago
- Limago: an FPGA-based Open-source 100 GbE TCP/IP Stack☆134Updated 4 years ago
- ☆79Updated 11 years ago
- ☆26Updated 4 years ago
- PCI Express controller model☆71Updated 3 years ago
- Verilog network module. Models network traffic from pcap to AXI-Stream☆22Updated 4 years ago
- BlackParrot on Zynq☆47Updated last week
- native Verilog pcap, littletoe, bcd, xml and hash modules, with Icarus testbenches☆46Updated 11 years ago
- OPAE porting to Xilinx FPGA devices.☆39Updated 5 years ago
- SystemVerilog DPI "TCP/IP Shunt" (System Verilog/SystemC/Python TCP/IP socket library)☆53Updated 4 months ago
- PCIe (1.0a to 2.0) Virtual Root Complex model for Verilog, with Endpoint capabilities☆127Updated last week