fixstars / xg_macLinks
10G Ethernet MAC implementation
☆21Updated 4 years ago
Alternatives and similar repositories for xg_mac
Users that are interested in xg_mac are comparing it to the libraries listed below
Sorting:
- Original FPGA platform☆66Updated last week
- Basic Common Modules☆39Updated last month
- An UGV-system using SoC-FPGA developed for FPGA design competition held on ICFPT2019☆17Updated 5 years ago
- RISC-V RV32IMAFC Core for MCU☆38Updated 4 months ago
- Source Codes for a lecture entitled "Parallel and Reconfigurable VLSI Computing" in Tokyo Tech.☆28Updated 4 years ago
- みんなのSystemVerilog☆19Updated 3 years ago
- FPGA+SoC+Linux+Device Tree Overlay+FPGA Manager U-Boot&Linux Kernel&Debian11 Images (for Xilinx:Zynq Ultrascale+ MPSoC)☆130Updated last year
- HOG + SVM on FPGA☆26Updated 4 years ago
- This is my first trial project for designing RISC-V in Chisel☆17Updated last year
- Ubuntu 18.04 Desktop for Ultra96/Ultra96-V2☆19Updated 5 years ago
- Implementation VexRiscv on ultra96☆12Updated 3 years ago
- Polyphony is Python based High-Level Synthesis compiler.☆105Updated 4 months ago
- Raspberry Pi v2 camera (IMX219) to DisplayPort of Ultra96-V2 board through PL☆70Updated 3 years ago
- Repository of HW design and SW for Ultra96 board + MIPI board☆17Updated 6 years ago
- The Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.☆45Updated 4 years ago
- SystemVerilog language server client for Visual Studio Code☆21Updated 2 years ago
- ☆53Updated 2 years ago
- Premade bitstreams and block designs to complemented the PYNQ overlay tutorial☆40Updated 3 years ago
- ☆26Updated 4 years ago
- ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…☆55Updated 3 weeks ago
- Board files to build Ultra 96 PYNQ image☆155Updated 6 months ago
- ☆45Updated 4 years ago
- FOS - FPGA Operating System☆68Updated 4 years ago
- Python-based Portable IP-core Synthesis Framework for FPGA-based Computing☆53Updated 8 years ago
- Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ☆33Updated 6 years ago
- Open Source PHY v2☆29Updated last year
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆63Updated 5 years ago
- This repository is no longer maintained. New repository is here(https://github.com/rggen/rggen).☆17Updated 5 years ago
- Open-source CSI-2 receiver for Xilinx UltraScale parts☆37Updated 5 years ago
- The Demo that was presented at FCCM.☆15Updated 6 years ago