Gabriele-bot / 100G-verilog-RoCEv2-liteView external linksLinks
TX only RoCEv2. Super stripped down version of a RoCEv2 endpoint.
☆41Updated this week
Alternatives and similar repositories for 100G-verilog-RoCEv2-lite
Users that are interested in 100G-verilog-RoCEv2-lite are comparing it to the libraries listed below
Sorting:
- The SoC Design for Time-Sensitive Networking (TSN)☆22Dec 5, 2025Updated 2 months ago
- ☆21Jul 28, 2021Updated 4 years ago
- ☆35Dec 10, 2023Updated 2 years ago
- ☆14May 15, 2023Updated 2 years ago
- TCL framework to package Vivado IP-Cores☆14May 18, 2022Updated 3 years ago
- PTPv2 hardware engine design for 10G Ethernet, described in Verilog HDL☆18May 27, 2025Updated 8 months ago
- Xilinx ZynqMP AXI-ACP Adapter☆20May 13, 2025Updated 9 months ago
- Chisel NVMe controller☆25Nov 24, 2022Updated 3 years ago
- DaCH: dataflow cache for high-level synthesis.☆20Jul 27, 2023Updated 2 years ago
- Xilinx PCIe to MIG DDR4 example designs and custom part data files☆40Feb 4, 2024Updated 2 years ago
- ☆21Apr 2, 2023Updated 2 years ago
- Checksum plays a key role in the TCP/IP headers. In this repo you'll find a efficient FPGA-based solution for a 512-bit AXI4-Stream inter…☆18Aug 28, 2019Updated 6 years ago
- Verilog Ethernet Switch (layer 2)☆51Oct 18, 2023Updated 2 years ago
- HW Design Collateral for Caliptra Subsystem, which comprises Caliptra RoT IP and additional manufacturer controls.☆38Updated this week
- An Open Source Link Protocol and Controller☆29Jul 26, 2021Updated 4 years ago
- CoRM: Compactable Remote Memory over RDMA☆20Jun 18, 2021Updated 4 years ago
- ☆20Jan 2, 2023Updated 3 years ago
- Build an open source, extremely simple DMA.☆23Feb 17, 2019Updated 7 years ago
- Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.☆29Nov 3, 2025Updated 3 months ago
- Framework providing operating system abstractions and a range of shared networking and memory services for common modern heterogeneous pl…☆326Updated this week
- IRN's packet processing logic synthesized using Xilinx Vivado HLS☆23Dec 14, 2018Updated 7 years ago
- Projects for building MIL-STD-1553 communications devices☆30Aug 7, 2024Updated last year
- Chisel implementation of Neural Processing Unit for System on the Chip☆26Jan 19, 2026Updated 3 weeks ago
- Software that implements a reliable high-performance control link for particle physics electronics, based on the IPbus protocol☆24Jan 7, 2026Updated last month
- ☆24Apr 18, 2021Updated 4 years ago
- Extensible FPGA control platform☆61Apr 28, 2023Updated 2 years ago
- Implementation of Wireless communication blocks such as FFT, OFDM receiver, Polar code decoder in a FPGA using Vivado HLS☆29Dec 17, 2020Updated 5 years ago
- There are the documents, floating and fixed-point algorithms, and Verilog codes for the project.☆11Jun 27, 2016Updated 9 years ago
- DPDK Drivers for AMD OpenNIC☆30Jul 20, 2023Updated 2 years ago
- ☆35Jun 9, 2022Updated 3 years ago
- JTAG DPI module for SystemVerilog RTL simulations☆32Oct 30, 2015Updated 10 years ago
- Networking Template Library for Vivado HLS☆28Jul 12, 2020Updated 5 years ago
- Computational Storage Device based on the open source project OpenSSD.☆30Oct 25, 2020Updated 5 years ago
- This is the source code for our (Tobias Ziegler, Jacob Nelson-Slivon, Carsten Binnig and Viktor Leis) published paper at SIGMOD’23: Desig…☆28Sep 24, 2024Updated last year
- Open source FPGA-based NIC and platform for in-network compute☆67Aug 21, 2025Updated 5 months ago
- An AXI DDR3 SDRAM controller for FPGA☆44Dec 30, 2023Updated 2 years ago
- ☆34Nov 26, 2019Updated 6 years ago
- Aquila: a 32-bit RISC-V processor for Xilinx FPGAs.☆37Oct 25, 2023Updated 2 years ago
- System-Veilog Packet Library to configure, randomize, pack/unpack, copy, compare/display different headers☆81Mar 6, 2019Updated 6 years ago