TX only RoCEv2. Super stripped down version of a RoCEv2 endpoint.
☆77Sep 30, 2026Updated 2 weeks ago
Alternatives and similar repositories for 100G-verilog-RoCEv2-lite
Users that are interested in 100G-verilog-RoCEv2-lite are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Framework providing operating system abstractions and a range of shared networking and memory services for common modern heterogeneous pl…☆463Updated this week
- ☆17Apr 7, 2026Updated 6 months ago
- RoCEv2 hardware implementation in Bluespec SystemVerilog☆37Feb 26, 2026Updated 7 months ago
- RecoNIC is a software/hardware shell used to enable network-attached processing within an RDMA-featured SmartNIC for scale-out computing.☆179Mar 20, 2025Updated last year
- Our contribution to the AMD Open Hardware Contest: A ML-based Deep Packet Inspection for RDMA-networking on FPGAs☆13May 6, 2026Updated 5 months ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- ☆42Jun 9, 2022Updated 4 years ago
- DPDK Drivers for AMD OpenNIC☆36Jul 20, 2023Updated 3 years ago
- ESnet general-purpose FPGA design library.☆14Updated this week
- Modified the conventional JPEG compression algorithm with Lloyd-Max Quantizer. Implemented in MATLAB and tested on Xilinx Artix-7 FPGA.☆18Aug 31, 2020Updated 6 years ago
- The SoC Design for Time-Sensitive Networking (TSN)☆25Dec 5, 2025Updated 10 months ago
- ☆14May 15, 2023Updated 3 years ago
- Verilog Ethernet Switch (layer 2)☆60Oct 18, 2023Updated 2 years ago
- ☆22Jul 28, 2021Updated 5 years ago
- Build an open source, extremely simple DMA.☆25Feb 17, 2019Updated 7 years ago
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- Network Development Kit (NDK) for FPGA cards with example application☆99Updated this week
- RPCNIC: A High-Performance and Reconfigurable PCIe-attached RPC Accelerator [HPCA2025]☆16Dec 9, 2024Updated last year
- ☆43Jul 4, 2026Updated 3 months ago
- AMD OpenNIC Shell includes the HDL source files☆159Jan 2, 2025Updated last year
- TCL framework to package Vivado IP-Cores☆13May 18, 2022Updated 4 years ago
- PCIe based accelerator for VCU1525 with xDMA based on Windows10 and Windows Server 2016 development environment☆58Feb 15, 2018Updated 8 years ago
- Software that implements a reliable high-performance control link for particle physics electronics, based on the IPbus protocol☆25Jan 7, 2026Updated 9 months ago
- Ethernet MAC IP Core for 100G/50G/40G/25G/10Gbps☆48Apr 3, 2023Updated 3 years ago
- ☆39Mar 10, 2021Updated 5 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Scalable Network Stack for FPGAs (TCP/IP, RoCEv2)☆972Aug 3, 2026Updated 2 months ago
- PTPv2 hardware engine design for 10G Ethernet, described in Verilog HDL☆19May 27, 2025Updated last year
- LeWiz Communications Ethernet MAC Core2 10G/5G/2.5G/1G☆42Apr 3, 2023Updated 3 years ago
- SystemVerilog AXI verification library and video-DMA IP: AXI4/Lite/Stream BFMs, triple-buffer VDMA, and multi-tap temporal VDMA with byte…☆29Jul 5, 2026Updated 3 months ago
- Xilinx Virtual Cable Server for Raspberry Pi☆127Mar 14, 2022Updated 4 years ago
- RISC-V soft-SoC extensible plaftorm for Xilinx FPGAs from University of Naples Federico II.☆20Oct 6, 2026Updated last week
- Microshift Compression: An Efficient Image Compression Algorithm for Hardware☆37Apr 21, 2021Updated 5 years ago
- Get Started From Here. The main repo for the whole open-rdma project. Including introduction, hands-on guide, new events and many other t…☆382Sep 1, 2026Updated last month
- ☆20Jul 6, 2023Updated 3 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- ☆17Dec 15, 2025Updated 10 months ago
- Firmware that implements a reliable high-performance control link for particle physics electronics, based on the IPbus protocol☆44Mar 5, 2026Updated 7 months ago
- CAN-bus Controller with AXI4-lite Interface☆17Mar 4, 2025Updated last year
- 将 Verilog 设计规范、流水线模式与 FPGA 优化笔记结构化为可查询的本地知识库，供本地智能代理或脚本检索并返回带出处的实现建议与示例代码。☆27May 23, 2026Updated 4 months ago
- AXI4-Compatible Verilog Cores, along with some helper modules.☆17Mar 14, 2020Updated 6 years ago
- ☆60Jul 11, 2024Updated 2 years ago
- The hardware implementation of UDP in Bluespec SystemVerilog☆14Jun 3, 2024Updated 2 years ago