0xArt / RGMII_Ethernet_Transceiver_Verilog
Verilog module to transmit/receive to/from RGMII compatible ethernet PHY
☆23Updated 2 years ago
Alternatives and similar repositories for RGMII_Ethernet_Transceiver_Verilog:
Users that are interested in RGMII_Ethernet_Transceiver_Verilog are comparing it to the libraries listed below
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆63Updated 4 years ago
- A simple Verilog SPI master / slave implementation featuring all 4 modes.☆53Updated 4 years ago
- UART -> AXI Bridge☆61Updated 3 years ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆49Updated last year
- Open-source high performance AXI4-based HyperRAM memory controller☆73Updated 2 years ago
- Interface Protocol in Verilog☆49Updated 5 years ago
- This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supp…☆51Updated 3 years ago
- SPI-Flash XIP Interface (Verilog)☆37Updated 3 years ago
- RTL Verilog library for various DSP modules☆86Updated 3 years ago
- Verilog SPI master and slave☆53Updated 9 years ago
- AHB DMA 32 / 64 bits☆54Updated 10 years ago
- ☆58Updated 2 years ago
- HW JPEG decoder wrapper with AXI-4 DMA☆34Updated 4 years ago
- Must-have verilog systemverilog modules☆33Updated 2 years ago
- SPI bus slave and flip-flop register memory map implemented in Verilog 2001 for FPGAs☆15Updated 5 years ago
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆68Updated 2 years ago
- A set of Wishbone Controlled SPI Flash Controllers☆79Updated 2 years ago
- ☆36Updated 9 years ago
- Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.☆34Updated last year
- Designing means to communicate as an SPI master, being a part of AXI interface☆17Updated last year
- SDRAM controller with AXI4 interface☆91Updated 5 years ago
- Implementation of JESD204B Transport Layer & part of Data Link Layer☆35Updated 3 years ago
- 100 MB/s Ethernet MAC Layer Switch☆14Updated 10 years ago
- Generic AXI to AHB bridge☆16Updated 10 years ago
- Engineering Program on RTL Design for FPGA Accelerator☆29Updated 4 years ago
- It is Gate level netlist of MAXVY's MIPI I3C Basic Master Controller IP along with APB interface support.☆16Updated 5 years ago
- configurable cordic core in verilog☆49Updated 10 years ago
- ☆25Updated 3 years ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆41Updated last year
- IP operations in verilog (simulation and implementation on ice40)☆55Updated 5 years ago