Alternatives and similar repositories for RGMII_Ethernet_Transceiver_Verilog

Users that are interested in RGMII_Ethernet_Transceiver_Verilog are comparing it to the libraries listed below

• ultraembedded / core_dbg_bridge
  UART -> AXI Bridge
  ☆63Updated 4 years ago
• OVGN / OpenHBMC
  Open-source high performance AXI4-based HyperRAM memory controller
  ☆79Updated 2 years ago
• ultraembedded / core_soc
  Basic Peripheral SoC (SPI, GPIO, Timer, UART)
  ☆66Updated 5 years ago
• someone755 / ddr3-controller
  A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs
  ☆74Updated 2 years ago
• alexforencich / cocotbext-uart
  UART models for cocotb
  ☆30Updated 3 weeks ago
• airhdl / spi-to-axi-bridge
  An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
  ☆50Updated last year
• ultraembedded / core_sdram_axi4
  SDRAM controller with AXI4 interface
  ☆98Updated 6 years ago
• freecores / ethmac
  Ethernet MAC 10/100 Mbps
  ☆84Updated 6 years ago
• ZipCPU / qspiflash
  A set of Wishbone Controlled SPI Flash Controllers
  ☆89Updated 2 years ago
• janschiefer / verilog_spi
  A simple Verilog SPI master / slave implementation featuring all 4 modes.
  ☆65Updated 4 years ago
• dirjud / Nitro-Parts-lib-SPI
  Verilog SPI master and slave
  ☆59Updated 9 years ago
• ultraembedded / core_ft60x_axi
  FTDI FT600 SuperSpeed USB3.0 to AXI bus master
  ☆94Updated 5 years ago
• alexforencich / verilog-lfsr
  Fully parametrizable combinatorial parallel LFSR/CRC module
  ☆157Updated 7 months ago
• alexforencich / cocotbext-i2c
  I2C models for cocotb
  ☆37Updated 3 weeks ago
• ultraembedded / core_spiflash
  SPI-Flash XIP Interface (Verilog)
  ☆45Updated 3 years ago
• hypernyan / eth_vlg
  ☆74Updated 3 years ago
• paulscherrerinstitute / psi_fpga_all
  Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.
  ☆39Updated 2 weeks ago
• www-asics-ws / usb2_dev
  USB 2.0 Device IP Core
  ☆69Updated 8 years ago
• damdoy / fpga_image_processing
  IP operations in verilog (simulation and implementation on ice40)
  ☆60Updated 5 years ago
• alexforencich / verilog-wishbone
  Verilog wishbone components
  ☆118Updated last year
• BrianHGinc / BrianHG-DDR3-Controller
  DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…
  ☆80Updated last year
• alexforencich / verilog-dsp
  Verilog digital signal processing components
  ☆156Updated 2 years ago
• freecores / mac_layer_switch
  100 MB/s Ethernet MAC Layer Switch
  ☆15Updated 11 years ago
• buttercutter / DDR
  A simple DDR3 memory controller
  ☆59Updated 2 years ago
• yigitbektasgursoy / SDRAM_Verilog
  Verilog HDL implementation of SDRAM controller and SDRAM model
  ☆30Updated last year
• jamieiles / uart
  Verilog UART
  ☆182Updated 12 years ago
• 0xArt / Tiny_But_Mighty_I2C_Master_Verilog
  I2C Master Verilog module
  ☆34Updated 4 months ago
• halftop / Interface-Protocol-in-Verilog
  Interface Protocol in Verilog
  ☆50Updated 6 years ago
• freecores / i2c
  I2C controller core
  ☆46Updated 2 years ago
• alknvl / axis_udp
  This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supp…
  ☆60Updated 3 years ago