Alternatives and similar repositories for Hardware-Security

Users that are interested in Hardware-Security are comparing it to the libraries listed below

• siamumar / BIST_PUF_TRNG
  A Built-in-Self-Test Scheme for Online Evaluation of Physical Unclonable Functions and True Random Number Generators
  ☆24Updated 8 years ago
• Crimsonninja / senior_design_puf
  Repository to store all design and testbench files for Senior Design
  ☆22Updated 5 years ago
• embecosm / chiphack
  Repository and Wiki for Chip Hack events.
  ☆52Updated 4 years ago
• colinoflynn / xdomain-dpa-m23
  Cross-Domain DPA Attack on SAML11
  ☆17Updated 6 years ago
• eriksargent / PUF-lab
  FPGA implementation of a physical unclonable function for authentication
  ☆33Updated 8 years ago
• stffrdhrn / uart
  Verilog uart receiver and transmitter modules for De0 Nano
  ☆18Updated 11 years ago
• sabbaghm / c-ll-verilog
  An LLVM based mini-C to Verilog High-level Synthesis tool
  ☆39Updated 9 months ago
• petrsocha / sicak
  SIde-Channel Analysis toolKit: embedded security evaluation tools
  ☆30Updated 3 years ago
• wisp / rfid-verilog
  RFID tag and tester in Verilog
  ☆41Updated 12 years ago
• ZipCPU / videozip
  A ZipCPU SoC for the Nexys Video board supporting video functionality
  ☆19Updated last year
• lowRISC / ot-sca
  Side-channel analysis setup for OpenTitan
  ☆37Updated last month
• florianbenz / bil
  Bitfile Interpretation Library for Xilinx Virtex FPGAs
  ☆28Updated 13 years ago
• betrusted-io / gateware
  IP submodules, formatted for easier CI integration
  ☆30Updated 2 months ago
• GOOD-Stuff / FPGA-SPI-Flash
  Various projects of SPI loader module for xilinx fpga
  ☆33Updated 5 years ago
• cw-leia / cw-leia-standalone-hard
  LEIA: the Lab Embedded ISO7816 Analyzer A Custom Smartcard Reader for the ChipWhisperer PCB
  ☆21Updated 4 years ago
• secworks / modexp
  Modular Exponentiation core written i Verilog. Supports key lengths between 32 and 8192 bits.
  ☆17Updated 5 years ago
• djn3m0 / debit
  Reverse-engineering tools for FPGA bitstreams, Altera and Xilinx
  ☆88Updated 10 years ago
• siliconcompiler / zerosoc
  Demo SoC for SiliconCompiler.
  ☆62Updated 3 weeks ago
• epfl-vlsc / bitfiltrator
  Bitfiltrator: A general approach for reverse-engineering Xilinx bitstream formats
  ☆48Updated 2 years ago
• KarenWest / hardwareSecurity
  hardware security course from Coursera and University of Maryland
  ☆28Updated 10 years ago
• scluconn / DA_PUF_Library
  Defense/Attack PUF Library (DA PUF Library)
  ☆54Updated 5 years ago
• gojimmypi / VerilogLanguageExtension
  Verilog Language Extension for Visual Studio
  ☆18Updated 4 years ago
• b224hisl / rioschip
  ☆33Updated 3 years ago
• enjoy-digital / pcie_analyzer
  PCIe analyzer experiments
  ☆63Updated 5 years ago
• ultraembedded / usb_sniffer
  High Speed USB 2.0 capture device based on miniSpartan6+
  ☆59Updated 5 years ago
• scarv / scarv
  SCARV: a side-channel hardened RISC-V platform
  ☆22Updated 4 years ago
• shiva-t / Elliptical-Curve-Cryptography-FPGA
  Implementation of ECC on FPGA-Zynq7000 SoC
  ☆19Updated 6 years ago
• unixb0y / SystemVerilogSHA256
  SHA256 in (System-) Verilog / Open Source FPGA Miner
  ☆83Updated 7 years ago
• ZipCPU / dbgbus
  A collection of debugging busses developed and presented at zipcpu.com
  ☆42Updated last year
• pothosware / PothosZynq
  DMA source and sink blocks for Xilinx Zynq FPGAs
  ☆23Updated 5 years ago