IamVNIE / Hardware-Security
Hardware Security Labs
☆30Updated 7 years ago
Alternatives and similar repositories for Hardware-Security:
Users that are interested in Hardware-Security are comparing it to the libraries listed below
- A Built-in-Self-Test Scheme for Online Evaluation of Physical Unclonable Functions and True Random Number Generators☆21Updated 7 years ago
- Repository to store all design and testbench files for Senior Design☆17Updated 4 years ago
- FPGA implementation of a physical unclonable function for authentication☆33Updated 7 years ago
- Side-channel analysis setup for OpenTitan☆29Updated last week
- Cross-Domain DPA Attack on SAML11☆15Updated 5 years ago
- Verilog implementation of 1024 bit Hybrid Montgomery Multiplication/Exponentiation☆10Updated 5 years ago
- RFID tag and tester in Verilog☆37Updated 11 years ago
- ☆20Updated 3 years ago
- An LLVM based mini-C to Verilog High-level Synthesis tool☆35Updated last year
- USB -> AXI Debug Bridge☆35Updated 3 years ago
- LEIA: the Lab Embedded ISO7816 Analyzer A Custom Smartcard Reader for the ChipWhisperer PCB☆19Updated 3 years ago
- A RISC-V SBC based around the LambdaConcept USB2Sniffer FPGA board.☆28Updated 4 years ago
- ☆18Updated last year
- Modular Exponentiation core written i Verilog. Supports key lengths between 32 and 8192 bits.☆17Updated 4 years ago
- Repository and Wiki for Chip Hack events.☆50Updated 3 years ago
- Dual RISC-V DISC with integrated eFPGA☆16Updated 3 years ago
- Implementation of ECC on FPGA-Zynq7000 SoC☆17Updated 5 years ago
- PCIe analyzer experiments☆49Updated 4 years ago
- The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freel…☆63Updated 2 years ago
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆52Updated 4 years ago
- An end-to-end chip authentication architecture based on SRAM PUF and public key cryptography.☆15Updated 5 years ago
- Verilog uart receiver and transmitter modules for De0 Nano☆18Updated 10 years ago
- FPGA gateware and pre-build bitstreams that expose SPI over JTAG. The protocol is implemented (among others) by openocd.☆53Updated last year
- RPHAX provides a quick automation flow to develop and prototype hardware accelerators on Xilinx FPGAs. Currently, the framework has suppo…☆17Updated last year
- True Random Number Generator core implemented in Verilog.☆74Updated 4 years ago
- Defense/Attack PUF Library (DA PUF Library)☆47Updated 4 years ago
- RISC-V Functional ISA Simulator☆14Updated 7 months ago
- SIde-Channel Analysis toolKit: embedded security evaluation tools☆28Updated 3 years ago
- ☆33Updated 2 years ago
- A VHDL IP for ECC (Elliptic Curve Cryptography) hardware acceleration☆35Updated 7 months ago