tkat0 / pynqmmult
"mmult" example using SDSoC for PYNQ board
☆11Updated 7 years ago
Related projects ⓘ
Alternatives and complementary repositories for pynqmmult
- Scripts to automate the process of building an image for the Xilinx PYNQ project. This repository is deprecated as its functionality is n…☆20Updated 7 years ago
- Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ☆33Updated 6 years ago
- Python-based Portable IP-core Synthesis Framework for FPGA-based Computing☆52Updated 8 years ago
- ☆28Updated 6 years ago
- Repository of HW design and SW for Ultra96 board + MIPI board☆17Updated 5 years ago
- Xilinx Contest Kshitij 2019☆19Updated last year
- Updated version of the XUP Workshops☆18Updated 6 years ago
- Matrix Operation Library for FPGA https://xilinx.github.io/gemx/☆63Updated 5 years ago
- HOG + SVM on FPGA☆25Updated 3 years ago
- A multi-board Extended Kalman Filter (EKF)☆28Updated 6 years ago
- The Shang high-level synthesis framework☆119Updated 10 years ago
- Networking Overlay on PYNQ☆44Updated 5 years ago
- ☆82Updated 4 years ago
- Python FIR Filter Package for Xilinx Pynq Board☆29Updated 6 years ago
- Adding PR to the PYNQ Overlay☆17Updated 7 years ago
- Premade bitstreams and block designs to complemented the PYNQ overlay tutorial☆39Updated 2 years ago
- Linear model training using stochastic gradient descent (SGD) on PYNQ with full to low precision.☆53Updated 6 years ago
- ☆23Updated 6 years ago
- Zynq PR Management☆11Updated 8 years ago
- openHMC - an open source Hybrid Memory Cube Controller☆44Updated 8 years ago
- Hot & Spicy tool suite☆23Updated 2 years ago
- ☆42Updated 3 years ago
- PYNQ-Z1 board files for Vivado☆32Updated 2 years ago
- Hand-written HDL code and C-based HLS designs for K-means clustering implementations on FPGAs☆47Updated 7 years ago
- A Tutorial on Putting High-Level Synthesis cores in PYNQ☆102Updated 6 years ago
- Xilinx Deep Learning IP☆92Updated 3 years ago
- Floating point modules for CHISEL☆28Updated 10 years ago
- ☆12Updated 5 years ago