fpgasystems / ZipML-PYNQ
Linear model training using stochastic gradient descent (SGD) on PYNQ with full to low precision.
☆53Updated 6 years ago
Related projects ⓘ
Alternatives and complementary repositories for ZipML-PYNQ
- Introductory examples for using PYNQ with Alveo☆48Updated last year
- Caffe to VHDL☆66Updated 4 years ago
- This repo is for ECE44x (Fall2015-Spring2016)☆19Updated 6 years ago
- CNN accelerator☆26Updated 7 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆24Updated 4 years ago
- MAESTRO binary release☆22Updated 5 years ago
- ☆55Updated 4 years ago
- ☆83Updated 5 months ago
- HLS implemented systolic array structure☆41Updated 7 years ago
- Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ☆52Updated 2 years ago
- FPGA-based stochastic gradient descent (powered by ZipML - Low-precision machine learning on reconfigurable hardware)☆33Updated 4 years ago
- ☆82Updated 4 years ago
- MAERI public release☆31Updated 3 years ago
- ☆70Updated last year
- Systolic-array based Deep Learning Accelerator generator☆24Updated 3 years ago
- ☆86Updated 4 years ago
- Systolic array based hardware for Image processing on the SPARTAN-6 FPGA☆12Updated 8 years ago
- Residual Binarized Neural Network☆44Updated 6 years ago
- Simple examples for FPGA design using Vivado HLS for high level synthesis and Vivado for bitstream generation.☆25Updated 4 years ago
- Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs☆158Updated last year
- Premade bitstreams and block designs to complemented the PYNQ overlay tutorial☆39Updated 2 years ago
- ☆40Updated 4 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆39Updated 4 years ago
- ☆28Updated 6 years ago
- Compact LSTM inference kernel (CLINK) designed in C/HLS for FPGA implementation.☆17Updated 5 years ago
- An LSTM template and a few examples using Vivado HLS☆42Updated 6 months ago
- The Verilog source code for DRUM approximate multiplier.☆28Updated last year
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆59Updated 3 years ago
- [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers☆29Updated 2 years ago