RyanMan1 / PYNQ-SVM-OpenHW-2020
A repository of my Xilinx Open Hardware 2020 submission including a demo of support vector machines on PYNQ, C++ source code and projects for HLS and tcl scripts to re-generate Vivado IPI overlay block designs.
☆16Updated 4 years ago
Alternatives and similar repositories for PYNQ-SVM-OpenHW-2020:
Users that are interested in PYNQ-SVM-OpenHW-2020 are comparing it to the libraries listed below
- Convolution Neural Network of vgg19 model in verilog☆46Updated 7 years ago
- AI Chip project☆25Updated 3 years ago
- Ultra96 PYNQ入门之一次简单的总结☆14Updated 4 years ago
- A Tutorial on Putting High-Level Synthesis cores in PYNQ☆104Updated 6 years ago
- Simple examples for FPGA design using Vivado HLS for high level synthesis and Vivado for bitstream generation.☆29Updated 4 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆36Updated 2 years ago
- The CNN based on the Xilinx Vivado HLS☆37Updated 3 years ago
- Huffman encoding core (Vivado HLS Project)☆12Updated 5 years ago
- This repository contains a "Hello World" introduction application to the Xilinx PYNQ framework.☆101Updated 2 years ago
- ☆63Updated 6 years ago
- AIChip 2021 project, NCKU☆18Updated 3 years ago
- HOG-SVM algorithm implemented in a Zynq 7000 SoC (Digilent ZYBO)☆15Updated 6 years ago
- Systolic-array based Deep Learning Accelerator generator☆25Updated 4 years ago
- This is the first step to implement RNN on FPGAs. All modules are heavily commented. We will use High-Level Synthesis to turn these code …☆22Updated 5 years ago
- Spiking neural network for Zynq devices with Vivado HLS☆33Updated 7 years ago
- PYNQ Composabe Overlays☆70Updated 9 months ago
- A simple demo to implement the Handwritten Mathematical Calculator on PYNQ-Z2 FPGA platform by using HLS.☆38Updated 4 years ago
- ☆14Updated 3 years ago
- CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations☆19Updated 7 years ago
- 基于HLS的高效深度卷积神经网络FPGA实现方法☆69Updated 5 years ago
- ☆16Updated 4 years ago
- ☆26Updated 4 years ago
- course design☆22Updated 7 years ago
- [FPGA-2022] N3H-Core: Neuron-designed Neural Network Accelerator via FPGA-based Heterogeneous Computing Cores☆12Updated 3 years ago
- tpu-systolic-array-weight-stationary☆23Updated 3 years ago
- This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems u…☆51Updated 6 years ago
- ☆32Updated 6 months ago
- This project implements a convolution kernel based on vivado HLS on zcu104☆37Updated 5 years ago
- DMA controller for CNN accelerator☆13Updated 7 years ago
- IMAGE PROCESSING ON XILINX PYNQ Z2 (CANNY, SOBEL)☆26Updated 3 years ago