A FPGA-based Accelerator for Shufflenetv2 implemented on Xillinx Zynq-7000 SoC
☆16Apr 22, 2019Updated 7 years ago
Alternatives and similar repositories for shufflenetv2_hls
Users that are interested in shufflenetv2_hls are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Codes to implement MobileNet V2 in a FPGA☆32Dec 21, 2020Updated 5 years ago
- YOLO example implementation using Intuitus CNN accelerator on ZYBO ZYNQ-7000 FPGA board☆23Jul 30, 2021Updated 5 years ago
- HLS code for a BNN accelerator☆17Sep 13, 2018Updated 8 years ago
- PyTorch implementation of DiracDeltaNet from paper Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs☆33May 30, 2019Updated 7 years ago
- Some attempts to build CNN on PYNQ.☆25Jun 28, 2019Updated 7 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- ☆14Jun 13, 2025Updated last year
- knowledge distillation for few-shot learning☆13Dec 27, 2023Updated 2 years ago
- Drop-in convolutional Kolmogorov-Arnold Network☆20May 23, 2024Updated 2 years ago
- ☆13Oct 6, 2023Updated 2 years ago
- ☆12Dec 20, 2019Updated 6 years ago
- 基于长短记忆型递归神经网络的水质预测模型☆11Aug 11, 2018Updated 8 years ago
- ☆14Oct 16, 2017Updated 8 years ago
- 基于Android NDK Osd实现,利用了SDL2_TTF把矢量字体转成bmp格式,然后把bmp转换成yuv格式,在YUV数据上做OSD叠加。☆10Jan 16, 2019Updated 7 years ago
- Learning Environment-aware and hardware-compatible beam-forming codebooks☆15Mar 8, 2020Updated 6 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- The community version of HLS_BLSTM (A BLSTM FPGA accelerator of an OCR appilcation, using CAPI/SNAP))☆11Sep 27, 2019Updated 7 years ago
- A parametric RTL code generator of an efficient integer MxM Systolic Array implementation for Xilinx FPGAs, with error detection capabili…☆15Aug 28, 2025Updated last year
- Export pytorch model to ONNX and convert ONNX from float32 to float 16☆11Feb 2, 2023Updated 3 years ago
- Implementation of YOLOv3-tiny + Depthwise Separable Convolution on FPGA☆34Mar 2, 2022Updated 4 years ago
- This is a repo listing papers/blogs/news related to CXL. Let's take the leap to Next-Gen memory system with the awesome CXL☆21Jul 10, 2024Updated 2 years ago
- This is an open CNN accelerator for everyone to use☆14Jul 15, 2019Updated 7 years ago
- [MIPR 2022 & TMM 2023] "Attentive Graph Neural Networks for Few-shot Learning" with its extension version☆16Apr 17, 2023Updated 3 years ago
- Vivado HLS study notes, courses, documents.☆13Dec 7, 2019Updated 6 years ago
- A repository of my Xilinx Open Hardware 2020 submission including a demo of support vector machines on PYNQ, C++ source code and projects…☆16Jun 27, 2020Updated 6 years ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- MTCNN with convolution reprogramed in c☆14Jul 25, 2019Updated 7 years ago
- An Synthesizable Deep Learning Library based on Xilinx High Level Synthesis(HLS) tool☆16Feb 20, 2017Updated 9 years ago
- 《嵌入式操作系统内核调度》一书的源码。本书不是讲解操作系统如何使用,而是使用汇编和C语言从无到有实现操作系统的多个功能。☆10Feb 7, 2023Updated 3 years ago
- Huffman encoding core (Vivado HLS Project)☆12Oct 15, 2019Updated 6 years ago
- Extracting Noise and Darkness: Low-Light Image Enhancement via Dual Prior Guidance☆15Aug 5, 2025Updated last year
- This program captures an image from a Linux video device (/dev/video0) and then displays and saves it using OpenCV4.☆13Feb 2, 2022Updated 4 years ago
- Feed-forward neural networks can be trained based on a gradient-descent based backpropagation algorithm. But, these algorithms require mo…☆12Jul 4, 2020Updated 6 years ago
- This code is implemeted for the papper "Real-Time Salient Closed Boundary Tracking via Line Segments Perceptual Grouping, Xuebin Qin, Shi…☆17Feb 5, 2018Updated 8 years ago
- This repo has codes for hardware accelerator design for CNNs using high level synthesis from Altera.☆13Dec 18, 2017Updated 8 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- mpp+h264+rga+live555++opencv+rtsp☆14Jun 17, 2020Updated 6 years ago
- a Real-time image recognition project with RTL accelerator and ZYNQ Architecture☆72Apr 8, 2024Updated 2 years ago
- ☆23May 25, 2023Updated 3 years ago
- Use Vivado on Mac without dual boot or laggy virtual machine☆18Mar 7, 2024Updated 2 years ago
- An HLS based winograd systolic CNN accelerator☆54Jul 18, 2021Updated 5 years ago
- 一个利用ANN(人工神经网络)和GA(遗传算法)实现污水排放溯源的个人项目。☆17Oct 30, 2020Updated 5 years ago
- BaseWavenet/Wavenet+ResidualBlock☆16Jan 21, 2019Updated 7 years ago