A FPGA-based Accelerator for Shufflenetv2 implemented on Xillinx Zynq-7000 SoC
☆16Apr 22, 2019Updated 6 years ago
Alternatives and similar repositories for shufflenetv2_hls
Users that are interested in shufflenetv2_hls are comparing it to the libraries listed below
Sorting:
- YOLO example implementation using Intuitus CNN accelerator on ZYBO ZYNQ-7000 FPGA board☆22Jul 30, 2021Updated 4 years ago
- HLS code for a BNN accelerator☆17Sep 13, 2018Updated 7 years ago
- Codes to implement MobileNet V2 in a FPGA☆30Dec 21, 2020Updated 5 years ago
- PyTorch implementation of DiracDeltaNet from paper Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs☆33May 30, 2019Updated 6 years ago
- Implementation of YOLOv3-tiny + Depthwise Separable Convolution on FPGA☆33Mar 2, 2022Updated 4 years ago
- Learning Environment-aware and hardware-compatible beam-forming codebooks☆15Mar 8, 2020Updated 6 years ago
- ☆11Jun 13, 2025Updated 8 months ago
- My blogs and code for machine learning. http://cnblogs.com/pinard☆13Jul 12, 2019Updated 6 years ago
- ☆12Apr 15, 2025Updated 10 months ago
- 🔥 大模型 & Agent 面试八股文完全指南 | LLM & Agent Interview Preparation Guide☆50Feb 28, 2026Updated last week
- A tool for extracting, modifying, and crafting ASDM binary packages (CVE-2022-20829)☆13Aug 15, 2022Updated 3 years ago
- Implementação de um Memory Pool usando Alocação Rápida.☆10Oct 2, 2021Updated 4 years ago
- Feed-forward neural networks can be trained based on a gradient-descent based backpropagation algorithm. But, these algorithms require mo…☆12Jul 4, 2020Updated 5 years ago
- 基于长短记忆型递归神经网络的水质预测模型☆11Aug 11, 2018Updated 7 years ago
- This repository is a collection of codes generated for optimizing the echo state network for RUL prediction of airplane engines☆10Oct 11, 2021Updated 4 years ago
- Vivado HLS study notes, courses, documents.☆12Dec 7, 2019Updated 6 years ago
- A frozen version of angr for the SAILR paper☆16Sep 4, 2024Updated last year
- 哈尔滨工业大学（深圳）2021年球季学期深度学习体系结构实验☆17Oct 1, 2022Updated 3 years ago
- 基于Android NDK Osd实现，利用了SDL2_TTF把矢量字体转成bmp格式，然后把bmp转换成yuv格式，在YUV数据上做OSD叠加。☆10Jan 16, 2019Updated 7 years ago
- ☆12Oct 6, 2023Updated 2 years ago
- A parametric RTL code generator of an efficient integer MxM Systolic Array implementation for Xilinx FPGAs, with error detection capabili…☆14Aug 28, 2025Updated 6 months ago
- TFA project for indirect call analysis☆10Mar 13, 2025Updated 11 months ago
- ☆15Mar 25, 2020Updated 5 years ago
- C++版本的sort算法，可无缝添加在检测器后进行实时多目标跟踪☆12Dec 1, 2022Updated 3 years ago
- ☆11Mar 22, 2022Updated 3 years ago
- FunProbe: Probing Functions from Binary Code through Probabilistic Analysis (ESEC/FSE '23)☆18Jun 21, 2025Updated 8 months ago
- 将xfeat导出为onnx模型，且输入图片可为任意大小☆13Jul 24, 2024Updated last year
- 挑战杯rk板端代码，gstreamer mpp硬解码，以及推理模型的rknn部署☆13Sep 12, 2023Updated 2 years ago
- Export pytorch model to ONNX and convert ONNX from float32 to float 16☆11Feb 2, 2023Updated 3 years ago
- 基4booth乘法器设计与验证☆15Apr 28, 2024Updated last year
- To create a data-web application deployed using the azure app service, which was made on Streamlit, the leading Pythonic data application…☆13Apr 2, 2022Updated 3 years ago
- An Synthesizable Deep Learning Library based on Xilinx High Level Synthesis(HLS) tool☆16Feb 20, 2017Updated 9 years ago
- MTCNN with convolution reprogramed in c☆14Jul 25, 2019Updated 6 years ago
- Proof of Concept for CVE-2021-1585: Cisco ASA Device Manager RCE☆13Aug 15, 2022Updated 3 years ago
- The implementation of state-of-the-art algorithms for finding the feature (detector and extractor) and matching between 2 images. It is d…☆12Aug 14, 2016Updated 9 years ago
- LeNet的C语言实现☆11Nov 21, 2019Updated 6 years ago
- Experiment code☆10Sep 17, 2018Updated 7 years ago
- FPGA-CNN Application for fruit detection based on Logos-PGL22G Board☆14Aug 24, 2022Updated 3 years ago
- Huffman encoding core (Vivado HLS Project)☆12Oct 15, 2019Updated 6 years ago