2268977258 / binocular-stitchingLinks
基于易灵思Ti60F225开发板和MT9M001双目摄像头,使用Verilog语言完成的双目拼接项目。摄像头输入图像数据后,在使用FAST计算图像特征点的同时,构建滑动窗口计算图像各个像素点的BRIEF描述符,完成后根据BRIEF描述符对两幅图像上的特征点进行暴力匹配,最后通过匹配结果计算拼接参数,完成图像的拼接。
☆17Updated 6 months ago
Alternatives and similar repositories for binocular-stitching
Users that are interested in binocular-stitching are comparing it to the libraries listed below
Sorting:
- 2023集创赛国二。基于脉动阵列写的一个简单的卷积层加速器,支持yolov3-tiny的第一层卷积层计算,可根据FPGA端DSP资源灵活调整脉动阵列的结构以实现不同的计算效率。☆202Updated this week
- upgrade to e203 (a risc-v core)☆45Updated 5 years ago
- A 16-bit by 16-bit signed binary multiplier based on the Radix-4 Booth algorithm and Wallace Tree reduction☆57Updated last year
- AXI总线连接器☆104Updated 5 years ago
- AXI协议规范中文翻译版☆164Updated 3 years ago
- CPU Design Based on RISCV ISA☆122Updated last year
- FPGA实现简单的图像处理算法☆61Updated 2 years ago
- Final Project of Software_Hardware_Co-Design_24Spring. FPGA-based RISC-V+ Convolutional Acceleration Unit.☆22Updated last year
- fpga跑sobel识别算法☆41Updated 4 years ago
- 清華大學 | 積體電路設計實驗 (IC LAB) | 110上☆45Updated 3 years ago
- Real time face detection based on Arm Cortex-M3 DesignStart and FPGA☆206Updated 2 years ago
- 我的数字IC厂库:Verilog HDL; System Vreilog; UVM; ModelSim; Quartus II;☆99Updated 3 years ago
- Mirror of william_william/uvm-mcdf on Gitee☆28Updated 2 years ago
- IC Verification & SV Demo☆54Updated 4 years ago
- AXI DMA 32 / 64 bits☆121Updated 11 years ago
- Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.☆132Updated 4 years ago
- 2022年全国大学生嵌入式芯片与系统设计竞赛——FPGA创新设计竞赛紫光同创赛道视频色度亮度提取赛题设计源文件☆39Updated 2 years ago
- 包含了SOC设计中的通用IP,如外设、总线结构、基础、验证等☆118Updated last week
- Radix-4 1024 point fft in verilog☆12Updated 5 years ago
- 数字IC秋招项目、手撕代码☆38Updated last year
- 2023集创赛紫光同创杯一等奖项目☆130Updated last year
- This is for uvm_tb_gen☆42Updated 8 months ago
- 【入门项目】基于PYNQ-Z2实现手写数字识别卷积神经网络硬件加速器☆169Updated 2 years ago
- verilog实现TPU中的脉动阵列计算卷积的module☆134Updated 5 months ago
- AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM an…☆181Updated 7 years ago
- Project is about designing a Trained Neural Network on FPGA to classify an Image Input using CNN.☆158Updated 4 years ago
- FPGA图像处理仿真平台☆27Updated 3 years ago
- MNIST using tensorflow, c++ and fpga (zynq7010)☆24Updated 2 years ago
- ☆69Updated 9 years ago
- An uvm verification env for ahb2apb bridge☆56Updated 4 years ago