基于易灵思Ti60F225开发板和MT9M001双目摄像头，使用Verilog语言完成的双目拼接项目。摄像头输入图像数据后，在使用FAST计算图像特征点的同时，构建滑动窗口计算图像各个像素点的BRIEF描述符，完成后根据BRIEF描述符对两幅图像上的特征点进行暴力匹配，最后通过匹配结果计算拼接参数，完成图像的拼接。
☆24Apr 16, 2025Updated last year
Alternatives and similar repositories for binocular-stitching
Users that are interested in binocular-stitching are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- 基于fpga的cordic算法实现☆13Oct 19, 2024Updated 2 years ago
- FPGA based, Real-time processing of audio, including voiceprint recognition, adaptive noise suppression, et al.☆18May 8, 2025Updated last year
- Checksum plays a key role in the TCP/IP headers. In this repo you'll find a efficient FPGA-based solution for a 512-bit AXI4-Stream inter…☆19Aug 28, 2019Updated 7 years ago
- 包含了SOC设计中的通用IP，如外设、总线结构、基础、验证等☆152Sep 17, 2026Updated last month
- Small API for visual tracking for testing different tracking techniques. Based on OpenCV 3.0☆10Feb 5, 2014Updated 12 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- ☆13Mar 8, 2024Updated 2 years ago
- 复微杯☆18Aug 7, 2024Updated 2 years ago
- Hardware implementation of HDR image producing algorithm☆16Sep 30, 2022Updated 4 years ago
- 第八届集创赛紫光同创杯国二FPGA部分☆37Sep 23, 2024Updated 2 years ago
- ☆12May 13, 2025Updated last year
- use Verilog HDL implemente bicubic interpolation in FPGA☆32Dec 31, 2019Updated 6 years ago
- ☆21Feb 25, 2024Updated 2 years ago
- This is a simple Risc-v core for software simulation on FPGA.☆10Apr 9, 2022Updated 4 years ago
- [TCL] - PNR - Innovus☆10Jun 15, 2023Updated 3 years ago
- Open source password manager - Proton Pass • AdSecurely store, share, and autofill your credentials with Proton Pass, the end-to-end encrypted password manager trusted by millions.
- A PWM Module IP core written in Verilog, along with a firmware driver (developed for the Zynq-7000 Programmable SoC)☆19Nov 3, 2014Updated 12 years ago
- Camera calibration via charuco board package☆15May 12, 2020Updated 6 years ago
- RISC-V Single-Cycle Processor Integrated With a Cache Memory System From RTL To GDS☆15Aug 26, 2024Updated 2 years ago
- ☆10Dec 15, 2023Updated 2 years ago
- Demonstration of a video processing design for the Digilent Zybo, using Web Camera for input and VGA interface for output.☆26Aug 28, 2016Updated 10 years ago
- 李忠《x86汇编语言：从实模式到保护模式》第2版检测点以及章节习题☆22Aug 24, 2023Updated 3 years ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆28Apr 18, 2019Updated 7 years ago
- kcf tracker of FPGA Accelerate☆10Jul 20, 2017Updated 9 years ago
- This repository contains a SDSoC Project which includes an implementation of a 3-layered artificial neural network (testphase only). It c…☆12Oct 7, 2016Updated 10 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- OV7670 Camera Module Initialize with XILINX ZYNQ Driver☆13Oct 22, 2016Updated 10 years ago
- ROS Implementation of the RRT*-Connect algorithm☆18Oct 31, 2019Updated 7 years ago
- 该文档是个人阅读学习蜂鸟E203源码的笔记☆15Aug 1, 2023Updated 3 years ago
- Multiple scale KCF tracker (matlab code)☆10Jun 20, 2017Updated 9 years ago
- 2020保研经验分享｜别留遗憾，也别后悔☆23Nov 1, 2021Updated 5 years ago
- FPGA Camera Parallel & MIPI Verilog☆36Nov 15, 2025Updated 11 months ago
- NTU Computer Architecture 2021 - CPU with Single issue, L1-cache☆11Jan 24, 2022Updated 4 years ago
- Study note about OpenCV StereoSGBM☆20Jan 18, 2017Updated 9 years ago
- TCL scripts for FPGA (Xilinx)☆36Jul 5, 2022Updated 4 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Bi Directional RRT* solver in ROS☆19Nov 18, 2018Updated 7 years ago
- 第四届全国大学生嵌入式比赛SoC☆12Apr 1, 2022Updated 4 years ago
- deep learning library with pipeline for MNIST classification, synthesizable on DE1 SoC FPGAs☆15Jan 15, 2025Updated last year
- ☆14Mar 13, 2023Updated 3 years ago
- 多特征(色调+边缘+纹理)融合的目标跟踪☆10Apr 24, 2018Updated 8 years ago
- 一个支持AXI总线、支持Cache、包括所有非浮点MIPS 1指令、支持例外的静态五级流水MIPS CPU☆11Oct 8, 2019Updated 7 years ago
- 2024年全国大学生嵌入式芯片与系统设计竞赛 FPGA创新设计赛道 国一+易灵思创新杯获奖作品 Ultra-Vision （基于Ti60F225的无极缩放算法实现）☆120Updated this week