IUST-Computer-Organization / LUMOS
Light Utilization with Multicycle Operational Stages (LUMOS) RISC-V Processor
☆48Updated 4 months ago
Alternatives and similar repositories for LUMOS:
Users that are interested in LUMOS are comparing it to the libraries listed below
- RISC-V Embedded Processor for Approximate Computing☆125Updated last week
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆86Updated last week
- ☆12Updated last month
- This repository contains the tasks performed for VL508- Physical Design of ASIC Course (Fall 2024)☆12Updated 5 months ago
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆42Updated 3 years ago
- Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…☆59Updated last year
- This repo is created to include illustrative examples on object oriented design pattern in SV☆56Updated 2 years ago
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆24Updated last year
- 5 Day TCL begginer to advanced training workshop by VSD☆17Updated last year
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆34Updated 2 years ago
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.☆57Updated last year
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆86Updated this week
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆23Updated 10 months ago
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆57Updated 2 years ago
- ☆28Updated last year
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆69Updated 2 years ago
- The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…☆24Updated 3 years ago
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆29Updated 2 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆66Updated 4 years ago
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆86Updated last year
- This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve…☆75Updated last year
- ☆40Updated 3 years ago
- In this workshop, we will delve into the process of designing an Application Specific Integrated Circuit (ASIC) from the Register Transf…☆11Updated 8 months ago
- Complete tutorial code.☆19Updated last year
- Structured UVM Course☆40Updated last year
- Verilog Design, Simulation & Synthesis of Digital ASIC Projects☆14Updated 2 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆65Updated 4 months ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆14Updated last year
- ☆10Updated 2 years ago
- Various RTL design blocks along with verification testbenches with SVAs. Designed using SystemVerilog☆25Updated 2 years ago