Synthesizable SystemVerilog IP-Core of the I2S Receiver
☆10Jun 7, 2020Updated 5 years ago
Alternatives and similar repositories for SV_I2S_RX_CORE
Users that are interested in SV_I2S_RX_CORE are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- I2S transciever implemented in Verilog HDL☆32Oct 11, 2017Updated 8 years ago
- i2s core, with support for both transmit and receive☆32May 24, 2018Updated 7 years ago
- Audio controller (I2S, SPDIF, DAC)☆95Sep 1, 2019Updated 6 years ago
- A Rust backend crate for the popular card game, Blackjack, designed to also be compiled for linking with C☆11Sep 17, 2019Updated 6 years ago
- ☆13Jun 4, 2020Updated 5 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting with the flexibility to host WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Cloudways by DigitalOcean.
- This is a repo containing ARM-Cortex-M0 based SOC designs implemented on the Nexus-4-DDR , Nexus-4 and the ARTY - A7 FPGA platforms.☆12Sep 6, 2023Updated 2 years ago
- Voice Recognition using FPGA-Based Neural Networks☆15Jul 6, 2016Updated 9 years ago
- A LiteX module implementing a USB UAC2 module with simple PDM in/out☆16Feb 16, 2022Updated 4 years ago
- Play a casual game of blackjack in the terminal. Written in Rust. 🂱🂫☆13Aug 22, 2022Updated 3 years ago
- Some documentation on the SNES PPUs☆15May 29, 2024Updated last year
- Effective Functions for mixed model☆13Jul 10, 2024Updated last year
- ☆15Jul 5, 2017Updated 8 years ago
- High-level synthesis (HLS) implementation of Sparse Matrix Vector Multiplication☆19Feb 17, 2022Updated 4 years ago
- A Global Positioning System (GPS) Disciplined Oscillator (DO)☆16Jan 3, 2021Updated 5 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click and start building anything your business needs.
- C SQ-Scanner-based project analyzed on SonarCloud using Travis☆13Apr 4, 2022Updated 3 years ago
- LSTM neural network (verilog)☆15Dec 5, 2018Updated 7 years ago
- A Python package to interface with a Keithley 2700 multimeter.☆10Aug 2, 2024Updated last year
- 关于数字IC的笔试面试题☆14Nov 17, 2019Updated 6 years ago
- Candy size USB to UART bridge.☆18Feb 18, 2021Updated 5 years ago
- ☆17Sep 28, 2017Updated 8 years ago
- Collection of notes and resources I created for some of the classes I took at CMU.☆14Jul 6, 2021Updated 4 years ago
- Various RTL design blocks along with verification testbenches with SVAs. Designed using SystemVerilog☆26Aug 11, 2022Updated 3 years ago
- A small rust library to copy files/folders from the project directory to the output directory☆17Dec 21, 2023Updated 2 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- 使用stm32f103系列实现的异步声卡，增加了CPLD外部时钟源（不再更新）☆11Feb 8, 2020Updated 6 years ago
- Digital Multimeter Control USB TCP RS232☆19Feb 23, 2023Updated 3 years ago
- Python software for laboratory instruments control and automation.☆10Nov 6, 2025Updated 4 months ago
- ☆11Nov 17, 2025Updated 4 months ago
- A SystemVerilog-based simulation and design of a Last Level Cache (LLC) implementing the MESI protocol, featuring Pseudo-LRU replacement,…☆15Mar 8, 2026Updated 3 weeks ago
- A Dual-Channel, Low Noise, Modular, 100 kHz Bandwidth, 24-Bit Data Acquisition (DAQ) Device / FFT Signal Analyzer☆15Sep 26, 2022Updated 3 years ago
- OpenDSP Service Core☆15Jun 23, 2025Updated 9 months ago
- ☆21Sep 26, 2025Updated 6 months ago
- a low cost adafruit macropad clone with integrated todbot MacroPadSynthPlug☆12Apr 14, 2023Updated 2 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- RISCV MYTH 4 stage pipelined core designed using TL-Verilog and supports RV32I base integer instruction set☆15Jan 14, 2021Updated 5 years ago
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆30Jun 27, 2022Updated 3 years ago
- FPGA-Based USB-Input Audio Digital to Analogue Converter☆17Jun 11, 2021Updated 4 years ago
- A Spark Photon-based WiFi/Microcontroller development board in the shape of an Arduino Uno.☆11Jun 29, 2021Updated 4 years ago
- A library that allows you to simulate Arduino program behavior and TFT output using Raylib☆13May 25, 2023Updated 2 years ago
- verilog example to drive PCM5102 DAC with FPGA☆18Apr 30, 2018Updated 7 years ago
- USB audio interface,design by STM32 and EP4CE6 FPGA,support DSD☆15Jan 20, 2017Updated 9 years ago