Alternatives and similar repositories for rv32I-TangNano9K:

Users that are interested in rv32I-TangNano9K are comparing it to the libraries listed below

• panda5mt / KyogenRV
  The Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.
  ☆44Updated 3 years ago
• ryuz / BinaryBrain
  Binary Neural Network Framework for FPGA(Differentiable LUT)
  ☆155Updated 4 months ago
• zf3 / psram-tang-nano-9k
  An open source PSRAM/HyperRAM controller for Sipeed Tang Nano 9K / Gowin GW1NR-LV9QN88PC6/15 FPGA
  ☆72Updated 2 years ago
• hamsternz / Rudi-RV32I
  A rudimental RISCV CPU supporting RV32I instructions, in VHDL
  ☆117Updated 4 years ago
• evantandersen / fpga-gpu
  A basic GPU for altera FPGAs
  ☆73Updated 5 years ago
• diningyo / dirv
  This is my first trial project for designing RISC-V in Chisel
  ☆17Updated 10 months ago
• nand2mario / ddr3-tang-primer-20k
  DDR3 controller for Tang Primer 20K (Gowin GW2A-18C fpga). DDR3-800 speed and low latency.
  ☆51Updated last year
• risclite / ARM9-compatible-soft-CPU-core
  This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone be…
  ☆79Updated 4 years ago
• kadomoto / poyo-v
  Open source RISC-V IP core for FPGA/ASIC design
  ☆30Updated 8 months ago
• ataradov / riscv
  Verilog implementation of a RISC-V core
  ☆110Updated 6 years ago
• x653 / xv6-riscv-fpga
  Build a RISC-V computer system on fpga iCE40HX8K-EVB and run UNIX xv6 using only FOSS (free and open source hard- and software).
  ☆45Updated 2 years ago
• AngeloJacobo / RISC-V
  Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
  ☆84Updated last year
• Kenji-Ishimaru / polyphony
  3D graphics rendering system for FPGA, the project contains hardware rasterizer, software geometry engine, and application middleware.
  ☆76Updated 4 years ago
• chadyuu / riscv-chisel-book
  ☆225Updated 2 years ago
• nand2mario / usb_hid_host
  A compact USB HID host FPGA core supporting keyboards, mice and gamepads.
  ☆121Updated this week
• AleksandarKostovic / Riscy-SoC
  Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog
  ☆79Updated 5 years ago
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆39Updated last month
• hi631 / tang-nano-9K
  ☆84Updated 2 years ago
• ryuz / jelly
  Original FPGA platform
  ☆62Updated this week
• tommythorn / yarvi
  Yet Another RISC-V Implementation
  ☆90Updated 6 months ago
• munetomo-maruyama / mmRISC-1
  RISC-V RV32IMAFC Core for MCU
  ☆36Updated last month
• chsasank / ARM7
  Implemetation of pipelined ARM7TDMI processor in Verilog
  ☆87Updated 6 years ago
• 4a1c0 / RV32i-Verilog
  Simple RiscV core for academic purpose.
  ☆22Updated 4 years ago
• alangarf / apple-one
  An attempt at a small Verilog implementation of the original Apple 1 on an FPGA
  ☆140Updated 11 months ago
• ultraembedded / core_usb_host
  Basic USB 1.1 Host Controller for small FPGAs
  ☆89Updated 4 years ago
• ultraembedded / exactstep
  Instruction set simulator for RISC-V, MIPS and ARM-v6m
  ☆94Updated 3 years ago
• stnolting / neorv32-verilog
  ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
  ☆77Updated this week
• ultraembedded / core_dvi_framebuffer
  Minimal DVI / HDMI Framebuffer
  ☆79Updated 4 years ago
• ash-olakangal / RISC-V-Processor
  Verilog implementation of multi-stage 32-bit RISC-V processor
  ☆94Updated 4 years ago
• Martoni / HdmiCore
  HDMI core in Chisel HDL
  ☆50Updated last year