eschkufz / cascadeLinks
A Just-In-Time Compiler for Verilog from VMware Research
☆22Updated 4 years ago
Alternatives and similar repositories for cascade
Users that are interested in cascade are comparing it to the libraries listed below
Sorting:
- Exploring gate level simulation☆58Updated 4 months ago
- A replacement for gtkwave, written in Rust with high-performance and larger-than-memory traces in mind.☆19Updated 3 years ago
- User-friendly explanation of Yosys options☆114Updated 3 years ago
- Dual-issue RV64IM processor for fun & learning☆64Updated 2 years ago
- Hot Reconfiguration Technology demo☆40Updated 3 years ago
- PicoRV☆44Updated 5 years ago
- System on Chip toolkit for Amaranth HDL☆92Updated 10 months ago
- End-to-end synthesis and P&R toolchain☆87Updated last week
- Mutation Cover with Yosys (MCY)☆86Updated this week
- Fiber-based SystemVerilog Simulator.☆25Updated 3 years ago
- mantle library☆44Updated 2 years ago
- Naive Educational RISC-V -- A simple single-stage RV32I processor☆27Updated 4 years ago
- MR1 formally verified RISC-V CPU☆53Updated 6 years ago
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆34Updated 4 years ago
- RISC-V Processor written in Amaranth HDL☆39Updated 3 years ago
- Industry standard I/O for Amaranth HDL☆29Updated 10 months ago
- Experiments with Yosys cxxrtl backend☆49Updated 7 months ago
- AXI Formal Verification IP☆20Updated 4 years ago
- USB virtual model in C++ for Verilog☆31Updated 10 months ago
- A Verilog Synthesis Regression Test☆37Updated last year
- Verilog FPGA Parts Library. Old Octavo soft-CPU project.☆75Updated 6 years ago
- LunaPnR is a place and router for integrated circuits☆47Updated last month
- Hardware generator debugger☆75Updated last year
- Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)☆37Updated 4 years ago
- RFCs for changes to the Amaranth language and standard components☆18Updated last month
- ☆56Updated 3 years ago
- The Critical Path - a rambly FPGA blog☆49Updated 5 years ago
- An FPGA reverse engineering and documentation project☆53Updated last week
- Reusable Verilog 2005 components for FPGA designs☆46Updated 6 months ago
- Next-Generation FPGA Place-and-Route☆10Updated 7 years ago