eschkufz / cascadeLinks
A Just-In-Time Compiler for Verilog from VMware Research
☆23Updated 5 years ago
Alternatives and similar repositories for cascade
Users that are interested in cascade are comparing it to the libraries listed below
Sorting:
- A replacement for gtkwave, written in Rust with high-performance and larger-than-memory traces in mind.☆19Updated 3 years ago
- Fiber-based SystemVerilog Simulator.☆25Updated 3 years ago
- End-to-end synthesis and P&R toolchain☆94Updated last month
- Exploring gate level simulation☆58Updated 9 months ago
- User-friendly explanation of Yosys options☆113Updated 4 years ago
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆35Updated 5 years ago
- Dual-issue RV64IM processor for fun & learning☆64Updated 2 years ago
- System on Chip toolkit for Amaranth HDL☆98Updated last year
- Hot Reconfiguration Technology demo☆42Updated 3 years ago
- MR1 formally verified RISC-V CPU☆56Updated 7 years ago
- An FPGA reverse engineering and documentation project☆65Updated this week
- PicoRV☆43Updated 5 years ago
- Experiments with Yosys cxxrtl backend☆50Updated last year
- Whisk: 16-bit serial processor for TT02☆13Updated last year
- RISC-V Processor written in Amaranth HDL☆39Updated 4 years ago
- Industry standard I/O for Amaranth HDL☆31Updated last year
- Next-Generation FPGA Place-and-Route☆10Updated 7 years ago
- mantle library☆44Updated 3 years ago
- Hardware generator debugger☆77Updated last year
- Verilator Porcelain☆49Updated 2 years ago
- Naive Educational RISC-V -- A simple single-stage RV32I processor☆27Updated 5 years ago
- RISC-V out-of-order core for education and research purposes☆81Updated last week
- Debuggable hardware generator☆70Updated 2 years ago
- RFCs for changes to the Amaranth language and standard components☆18Updated this week
- Reusable Verilog 2005 components for FPGA designs☆49Updated last month
- A Verilog Synthesis Regression Test☆37Updated last week
- Mutation Cover with Yosys (MCY)☆90Updated 2 weeks ago
- USB virtual model in C++, co-simulating with Verilog, SystemVerilog and VHDL☆32Updated last year
- VS Code based debugger for hardware designs in Amaranth or Verilog☆39Updated last year
- ☆27Updated 11 months ago