The project involves the design of a 4X4 (16-bit) SRAM Memory Array using Cadence Virtuoso
☆56Mar 21, 2024Updated last year
Alternatives and similar repositories for Memory-Design-And-Testing
Users that are interested in Memory-Design-And-Testing are comparing it to the libraries listed below
Sorting:
- Design and Simulation of 1K * 32 bit SRAM memory design.☆17Dec 15, 2021Updated 4 years ago
- This repository is dedicated to VLSI ASIC Design Flow using open-source tools! Here, we embark on a journey that starts with specificatio…☆27Jan 23, 2024Updated 2 years ago
- A FIFO or Queue is an array of memory commonly used in hardware to transfer transfer data between two circuits with different clocks. The…☆16Nov 5, 2017Updated 8 years ago
- This project shows how to model a 4-bit flash ADC and a 4-bit DAC using ideal components. Used vdc, vpulse, vcvs, switch, res, cap, vccs …☆18Apr 20, 2019Updated 6 years ago
- This project is about building a Clocked Comparator to be used in a 4-bit Flash ADC & minimize the ADC Figure of Merit given by FoM = Pow…☆15Sep 12, 2023Updated 2 years ago
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.☆108Feb 22, 2024Updated 2 years ago
- This project shows the design of two 4-bit current steering DACs, based on Binary and Segmented architectures at VDD=1.8V supply, using h…☆24May 2, 2025Updated 10 months ago
- This project shows how to model a 10-bit pipeline ADC and a 10-bit DAC using ideal components. Used vdc, vpulse, vcvs, switch, res, cap, …☆36Apr 7, 2019Updated 6 years ago
- ☆48Apr 7, 2024Updated last year
- This repository includes the Resistive Random Access Memory (RRAM) Compiler which is designed in the context of the research project of D…☆78Oct 10, 2022Updated 3 years ago
- Lightening-Transformer: A Dynamically-operated Optically-interconnected Photonic Transformer Accelerator, HPCA'24☆40Feb 5, 2025Updated last year
- ☆33Nov 27, 2023Updated 2 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆82May 2, 2021Updated 4 years ago
- DEsign 16-bit ALU using Verilog☆10Feb 13, 2016Updated 10 years ago
- ☆12Jul 7, 2020Updated 5 years ago
- ☆87Jan 15, 2025Updated last year
- This project is about designing a 1.5 bit stage Pipeline ADC & the OpAmp required for its MDAC.☆39Mar 2, 2022Updated 4 years ago
- repository for a bandgap voltage reference in SKY130 technology☆42Jan 20, 2023Updated 3 years ago
- Portal for 2024 SIT batch being mentored at the Advnaced VLSI Lab.☆11Apr 9, 2023Updated 2 years ago
- MD5 in VHDL☆11Jan 4, 2017Updated 9 years ago
- UVM☆13Mar 16, 2020Updated 5 years ago
- Integrated Circuit Design - IC Design Flow and Project-Based Learning☆34Feb 27, 2026Updated last week
- Vehicle templates with multibody suspension and electric powertrain sized for Formula Student competitions.☆15Feb 25, 2026Updated last week
- A plugin to allow Jenkins Steps with Cadence vManager API☆10Jan 15, 2026Updated last month
- This project was done as a part of Beginner VLSI/SoC Physical design using open-source EDA Tools workshop.☆11Nov 23, 2020Updated 5 years ago
- Innervator: Hardware Acceleration for Neural Networks☆18Aug 3, 2024Updated last year
- This repository contains the details and the code for the MIPS32 ISA based RISC Processor, which is implemented in 5 stage pipelined conf…☆17Apr 26, 2023Updated 2 years ago
- Go Board FPGA Project for Ambient Light Sensor in VHDL and Verilog☆10Apr 20, 2019Updated 6 years ago
- Post-quantum cryptography (PQC) - Falcon☆14Apr 15, 2025Updated 10 months ago
- [TVLSI 2025] ACiM Inference Simulation Framework in "ASiM: Modeling and Analyzing Inference Accuracy of SRAM-Based Analog CiM Circuits"☆27Sep 9, 2025Updated 5 months ago
- Git clone of the FVWM CVS repository.☆23Mar 13, 2016Updated 9 years ago
- Tensor Processing Unit implementation in Verilog☆13Mar 18, 2025Updated 11 months ago
- 基于FP16的二维脉动阵列电路设计☆13Feb 23, 2023Updated 3 years ago
- All design files, source code, and documentation for Project OAK, a digital watch inspired by mechanical complications.☆25Dec 14, 2025Updated 2 months ago
- Parametric GPIO Peripheral☆12Jan 30, 2025Updated last year
- HPC Python Workshop at RSECon22☆14Oct 17, 2022Updated 3 years ago
- Design and UVM Verification of an ALU☆10Jun 14, 2024Updated last year
- Design of an image generator to represent a street scene. Can be used as a stand-alone design for image generator or as a test pattern ge…☆11Nov 18, 2019Updated 6 years ago
- An SRAM IP Uniquely designed with open source tools. Static RAM is a type of random-access memory that uses latching circuitry (flip-flop…☆14Jul 22, 2020Updated 5 years ago