The project involves the design of a 4X4 (16-bit) SRAM Memory Array using Cadence Virtuoso
☆62Mar 21, 2024Updated 2 years ago
Alternatives and similar repositories for Memory-Design-And-Testing
Users that are interested in Memory-Design-And-Testing are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- This repository is dedicated to VLSI ASIC Design Flow using open-source tools! Here, we embark on a journey that starts with specificatio…☆34Jan 23, 2024Updated 2 years ago
- The project is about building an 8-row by 8-bit 6T SRAM memory array, & a 3-to-8 decoder that's used to access the SRAM array. The layout…☆91Mar 19, 2026Updated 2 months ago
- This project offers an immersive tutorial experienced within the context of the Advanced Physical Design, focusing on the utilization of …☆38Sep 21, 2023Updated 2 years ago
- A FIFO or Queue is an array of memory commonly used in hardware to transfer transfer data between two circuits with different clocks. The…☆16Nov 5, 2017Updated 8 years ago
- This repository contains a detailed description of how to generate parameterized cells using GDSFactory-based layout automation tool GLay…☆13Oct 14, 2024Updated last year
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- This project shows how to model a 4-bit flash ADC and a 4-bit DAC using ideal components. Used vdc, vpulse, vcvs, switch, res, cap, vccs …☆21Apr 20, 2019Updated 7 years ago
- This project is about building a Clocked Comparator to be used in a 4-bit Flash ADC & minimize the ADC Figure of Merit given by FoM = Pow…☆17Sep 12, 2023Updated 2 years ago
- ☆21Aug 4, 2022Updated 3 years ago
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.☆119Feb 22, 2024Updated 2 years ago
- This project shows the design of two 4-bit current steering DACs, based on Binary and Segmented architectures at VDD=1.8V supply, using h…☆26May 2, 2025Updated last year
- This repository includes the Resistive Random Access Memory (RRAM) Compiler which is designed in the context of the research project of D…☆81Oct 10, 2022Updated 3 years ago
- ☆36Nov 27, 2023Updated 2 years ago
- [TVLSI 2025] ACiM Inference Simulation Framework in "ASiM: Modeling and Analyzing Inference Accuracy of SRAM-Based Analog CiM Circuits"☆29Sep 9, 2025Updated 9 months ago
- Tensor Processing Unit implementation in Verilog☆14Mar 18, 2025Updated last year
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- This project shows how to model a 10-bit pipeline ADC and a 10-bit DAC using ideal components. Used vdc, vpulse, vcvs, switch, res, cap, …☆39Apr 7, 2019Updated 7 years ago
- awesome-Analog-IC-Design-Automation☆55Apr 19, 2023Updated 3 years ago
- This repository contains the details and the code for the MIPS32 ISA based RISC Processor, which is implemented in 5 stage pipelined conf…☆19Apr 26, 2023Updated 3 years ago
- This project is about designing a 1.5 bit stage Pipeline ADC & the OpAmp required for its MDAC.☆44Mar 2, 2022Updated 4 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆85May 2, 2021Updated 5 years ago
- ☆32Updated this week
- 基于FP16的二维脉动阵列电路设计☆13Feb 23, 2023Updated 3 years ago
- Implementation for paper "BATMANN: A Binarized-All-Through Memory-Augmented Neural Network for Efficient In-Memory Computing"☆12Jan 12, 2022Updated 4 years ago
- ☆48Apr 7, 2024Updated 2 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆58Jul 9, 2021Updated 4 years ago
- Getting started with RISC-V☆14Jun 4, 2023Updated 3 years ago
- repository for a bandgap voltage reference in SKY130 technology☆44Jan 20, 2023Updated 3 years ago
- ☆14Sep 27, 2022Updated 3 years ago
- ☆12Jul 7, 2020Updated 5 years ago
- An SRAM IP Uniquely designed with open source tools. Static RAM is a type of random-access memory that uses latching circuitry (flip-flop…☆14Jul 22, 2020Updated 5 years ago
- All design files, source code, and documentation for Project OAK, a digital watch inspired by mechanical complications.☆26Dec 14, 2025Updated 6 months ago
- ☆12Dec 11, 2023Updated 2 years ago
- MD5 in VHDL☆11Jan 4, 2017Updated 9 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- ☆15May 8, 2018Updated 8 years ago
- Lightening-Transformer: A Dynamically-operated Optically-interconnected Photonic Transformer Accelerator, HPCA'24☆44Feb 5, 2025Updated last year
- ☆22May 21, 2023Updated 3 years ago
- DEsign 16-bit ALU using Verilog☆10Feb 13, 2016Updated 10 years ago
- Innervator: Hardware Acceleration for Neural Networks☆21Aug 3, 2024Updated last year
- ☆14Sep 4, 2025Updated 9 months ago
- ☆12Jun 8, 2018Updated 8 years ago