VardhanSuroshi / Memory-Design-And-Testing
The project involves the design of a 4X4 (16-bit) SRAM Memory Array using Cadence Virtuoso
☆18Updated 10 months ago
Alternatives and similar repositories for Memory-Design-And-Testing:
Users that are interested in Memory-Design-And-Testing are comparing it to the libraries listed below
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.☆36Updated 11 months ago
- The project is about building an 8-row by 8-bit 6T SRAM memory array, & a 3-to-8 decoder that's used to access the SRAM array. The layout…☆69Updated 2 years ago
- This project shows the design of a frequency synthesizer PLL system that produces a 1.92 GHz signal with a reference input of 30 MHz, wit…☆62Updated last year
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆64Updated 3 years ago
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆64Updated 4 years ago
- ☆40Updated 2 years ago
- 5 Day TCL begginer to advanced training workshop by VSD☆16Updated last year
- This repository contains all the contents studied and created during the Advanced Physical Design Workshop using OpenLANE and SKY130 PDK☆37Updated 2 years ago
- This project describes how the PNR of an analog IP, 2:1 analog multiplexer is carried out by opensource EDA tools, Openlane. It also disc…☆42Updated 4 years ago
- In this workshop, we will delve into the process of designing an Application Specific Integrated Circuit (ASIC) from the Register Transf…☆9Updated 5 months ago
- Static Timing Analysis Full Course☆47Updated 2 years ago
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆51Updated 2 years ago
- This project produces a clean GDSII Layout with all its details that are used to print photomasks used in the fabrication of a behavioral…☆13Updated 3 years ago
- This repository presents ASIC design flow for UART utilizing RTL to GDS implementation This has been simulated on VCS and has been impl…☆15Updated 9 months ago
- UVM and System Verilog Manuals☆39Updated 5 years ago
- This project is about building a Clocked Comparator to be used in a 4-bit Flash ADC & minimize the ADC Figure of Merit given by FoM = Pow…☆14Updated last year
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆41Updated 3 years ago
- This project shows how to design a clock bootstrapped circuit to improve the nonlinearity of the switch used in Track & Hold circuit. A c…☆10Updated 5 years ago
- The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…☆53Updated 2 years ago
- ☆12Updated last year
- Tests for the design flow with Synopsys tools for the implementation of a RISC-V processor.☆18Updated 4 months ago
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆21Updated last year
- ☆38Updated 3 years ago
- Asynchronous fifo in verilog☆32Updated 8 years ago
- This project shows how to model a 4-bit flash ADC and a 4-bit DAC using ideal components. Used vdc, vpulse, vcvs, switch, res, cap, vccs …☆13Updated 5 years ago
- Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…☆54Updated 9 months ago
- ☆16Updated last year
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆32Updated 2 years ago
- Ancillary Material for the book "Systematic Design of Analog CMOS Circuits"☆115Updated 10 months ago
- DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision☆42Updated 10 months ago