chennakeshavadasa / Miller-Compensated-Two-stage-OPAMP-using-SKY130PDKLinks
Design of miller compensated 2 stage opamp using open source SKY130PDK
☆13Updated 5 months ago
Alternatives and similar repositories for Miller-Compensated-Two-stage-OPAMP-using-SKY130PDK
Users that are interested in Miller-Compensated-Two-stage-OPAMP-using-SKY130PDK are comparing it to the libraries listed below
Sorting:
- ☆83Updated 10 months ago
- EE 628: Analysis and Design of Integrated Circuits (University of Hawaiʻi at Mānoa)☆169Updated 3 months ago
- ☆109Updated last week
- Solve one design problem each day for a month☆49Updated 2 years ago
- Python script for generating lookup tables for the gm/ID design methodology and much more ...☆108Updated last week
- repository for a bandgap voltage reference in SKY130 technology☆41Updated 2 years ago
- PLL Designs on Skywater 130nm MPW☆22Updated last year
- Ancillary Material for the book "Systematic Design of Analog CMOS Circuits"☆169Updated last month
- SG13G2_ASIC-Design-Template☆15Updated 4 months ago
- This repository contains all the contents studied and created during the Advanced Physical Design Workshop using OpenLANE and SKY130 PDK☆44Updated 3 years ago
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆67Updated 3 years ago
- JKU IIC OSIC-Multitool for open-source IC (OSIC) design for SKY130.☆75Updated 8 months ago
- A python3 gm/ID starter kit☆56Updated 3 months ago
- This project discusses the design of an 8-bit asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) impl…☆184Updated last year
- FOSS-ASIC-TOOLS is all in one container for SKY130 based design both Analog and Digital. Below is a list of the current tools already ins…☆104Updated last year
- This project shows the design of a frequency synthesizer PLL system that produces a 1.92 GHz signal with a reference input of 30 MHz, wit…☆78Updated 2 years ago
- Sandbox for experimenting with Ngspice and open PDKs in Google Colab☆26Updated last year
- This repository in a walk through the entire process of PLL IC designing from the tools to the final tapeout.☆20Updated 3 years ago
- ☆15Updated 2 years ago
- This project is about building a high FOM 2.4 GHz LNA for Bluetooth Low-Energy (BLE) Standards, using 45nm CMOS technology.☆12Updated 6 years ago
- In this workshop, we will delve into the process of designing an Application Specific Integrated Circuit (ASIC) from the Register Transf…☆15Updated last year
- This project produces a clean GDSII Layout with all its details that are used to print photomasks used in the fabrication of a behavioral…☆14Updated 4 years ago
- The project is about building an 8-row by 8-bit 6T SRAM memory array, & a 3-to-8 decoder that's used to access the SRAM array. The layout…☆81Updated 3 years ago
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆75Updated 5 years ago
- Two Stage CMOS Operational Amplifier IP Design using Skywater 130nm Technology☆22Updated 3 years ago
- Python port of Prof. Boris Murmann's gm/ID Starter Kit☆54Updated 8 years ago
- This project shows how to model a 10-bit pipeline ADC and a 10-bit DAC using ideal components. Used vdc, vpulse, vcvs, switch, res, cap, …☆35Updated 6 years ago
- ☆43Updated 3 years ago
- This repo contains introduction of gm/id method and its application to some OTA design examples.☆18Updated last year
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.☆92Updated last year