AngeloJacobo / DDR3-Notes
My notes for DDR3 SDRAM controller
☆33Updated 2 years ago
Alternatives and similar repositories for DDR3-Notes:
Users that are interested in DDR3-Notes are comparing it to the libraries listed below
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆103Updated 3 years ago
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆69Updated 2 years ago
- SystemVerilog frontend for Yosys☆100Updated last week
- A simple DDR3 memory controller☆54Updated 2 years ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆54Updated 3 months ago
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆86Updated this week
- IEEE P1735 decryptor for VHDL☆31Updated 9 years ago
- ☆59Updated 3 years ago
- PCIe (1.0a to 2.0) Virtual Root Complex model for Verilog, with Endpoint capabilities☆96Updated last month
- Re-coded Xilinx primitives for Verilator use☆48Updated last year
- A set of Wishbone Controlled SPI Flash Controllers☆80Updated 2 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆98Updated last month
- ☆21Updated this week
- Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples =>…☆61Updated this week
- Open-source high performance AXI4-based HyperRAM memory controller☆74Updated 2 years ago
- SDRAM controller with AXI4 interface☆92Updated 5 years ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆62Updated last year
- Bitstream relocation and manipulation tool.☆44Updated 2 years ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆114Updated last year
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆86Updated last week
- Easy-to-use JTAG TAP and Debug Controller core written in Verilog☆28Updated 6 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆63Updated 5 years ago
- Generic FIFO implementation with optional FWFT☆57Updated 4 years ago
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆31Updated last year
- Repository gathering basic modules for CDC purpose☆53Updated 5 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆65Updated 4 months ago
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆65Updated 8 months ago
- General Purpose AXI Direct Memory Access☆49Updated 11 months ago
- pulp_soc is the core building component of PULP based SoCs☆79Updated last month
- UART -> AXI Bridge☆61Updated 3 years ago