My notes for DDR3 SDRAM controller
☆57Feb 23, 2023Updated 3 years ago
Alternatives and similar repositories for DDR3-Notes
Users that are interested in DDR3-Notes are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Opensource DDR3 Controller☆485Sep 12, 2026Updated last month
- DDR3 controller for Tang Primer 20K (Gowin GW2A-18C fpga). DDR3-800 speed and low latency.☆76Jul 25, 2023Updated 3 years ago
- Re-coded Gowin GW1N primitives for Verilator use☆24Aug 19, 2022Updated 4 years ago
- The hardware implementation of UDP in Bluespec SystemVerilog☆14Jun 3, 2024Updated 2 years ago
- Our project involves the design of an 8-bit microprocessor data-path including 8-byte dual port memory, ALU and barrel shifter using CMOS…☆16Jan 2, 2021Updated 5 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- MediaTek MD32 processor module for Ghidra.☆16Apr 10, 2024Updated 2 years ago
- Build edk2 development and debugging environment under win10, for recording some notes and writing self tools.☆13Aug 14, 2022Updated 4 years ago
- This is a repo containing ARM-Cortex-M0 based SOC designs implemented on the Nexus-4-DDR , Nexus-4 and the ARTY - A7 FPGA platforms.☆12Sep 6, 2023Updated 3 years ago
- Fast parser for Saleae Logic 2 binary export format (Digital only)☆22Mar 31, 2025Updated last year
- A Python-based HDL and framework for silicon-based witchcraft☆43Sep 12, 2026Updated last month
- Post-synthesis power optimization via dual-Vth cell assignment and gate re-sizing. Scripting in TCL with custom commands written for Syno…☆14Jun 9, 2021Updated 5 years ago
- XTRX LiteX/LitePCIe based design for Julia Computing☆27Mar 11, 2024Updated 2 years ago
- PCIe to .1 inch header breakout☆11Sep 14, 2020Updated 6 years ago
- Realtime depth map 🏞️ generation using SSD algorithm on low end Basys 3 FPGA. Support 320x240 and 160x120 resolutions.☆22Feb 8, 2023Updated 3 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- ☆18Apr 7, 2022Updated 4 years ago
- PCIe stack written in Amaranth.☆18Apr 27, 2026Updated 5 months ago
- ☆13Dec 1, 2024Updated last year
- Project Peppercorn GateMate Test Cases☆19Sep 29, 2026Updated 2 weeks ago
- ☆118Jan 22, 2023Updated 3 years ago
- The project is a simple example about how to use TensorFlow to train a ConNet model from labeled dataset and then use Vitis AI tools to d…☆16Aug 15, 2020Updated 6 years ago
- A DDR3 memory controller in Verilog for various FPGAs☆640Oct 10, 2021Updated 5 years ago
- MiniJVM is a stupidly simple JVM written in C for reverse-engineering purposes.☆18Jun 27, 2026Updated 3 months ago
- The first-ever opensource soft core for PCIE EndPoint. Without vendor-locked HMs for Data Link, Transaction, Application layers. With sta…☆99Updated this week
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- Open source FPGA-based NIC and platform for in-network compute☆18May 22, 2024Updated 2 years ago
- Files and documentation for Pico-Dirty-Blaster Workshop☆20Jun 21, 2025Updated last year
- SystemVerilog AXI verification library and video-DMA IP: AXI4/Lite/Stream BFMs, triple-buffer VDMA, and multi-tap temporal VDMA with byte…☆27Jul 5, 2026Updated 3 months ago
- Learn and build GPU RTL from scratch☆22Aug 1, 2025Updated last year
- Chisel NVMe controller☆29Nov 24, 2022Updated 3 years ago
- A simple C++ CMake project to jump-start development of SystemC models and systems☆31Nov 24, 2024Updated last year
- Schoko Computer☆11Jun 7, 2023Updated 3 years ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆22Mar 22, 2023Updated 3 years ago
- Fully-differential asynchronous non-binary 12-bit SAR-ADC in SKY130, free to re-use under Apache-2.0 license☆68Mar 13, 2025Updated last year
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.☆38May 7, 2024Updated 2 years ago
- A simple OpenGL 3.2 example using MSVS 2010 and freeglut☆12Feb 4, 2013Updated 13 years ago
- ☆16Jun 28, 2021Updated 5 years ago
- An open source CPU design and verification platform for academia☆126Aug 22, 2025Updated last year
- ☆12Jul 2, 2021Updated 5 years ago
- Verilog design files and Icestudio file for streaming the OV7670 camera using ULX3S FPGA Board☆25Nov 17, 2021Updated 4 years ago
- CVE-2021-39685 Description and sample exploit for Linux USB Gadget overflow vulnerability☆14Apr 28, 2022Updated 4 years ago