AngeloJacobo / DDR3-NotesLinks
My notes for DDR3 SDRAM controller
☆43Updated 2 years ago
Alternatives and similar repositories for DDR3-Notes
Users that are interested in DDR3-Notes are comparing it to the libraries listed below
Sorting:
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆78Updated 3 years ago
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆121Updated 4 years ago
- A simple DDR3 memory controller☆61Updated 2 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆81Updated 3 years ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆120Updated 2 years ago
- RISC-V Nox core☆71Updated 5 months ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆124Updated 5 months ago
- A demo system for Ibex including debug support and some peripherals☆85Updated 2 months ago
- FuseSoC standard core library☆151Updated last month
- The Open Source Hardware Accelerator for Efficient Neural Network Inference☆48Updated last week
- IEEE P1735 decryptor for VHDL☆39Updated 10 years ago
- UART -> AXI Bridge☆68Updated 4 years ago
- PCIe (1.0a to 2.0) Virtual Root Complex model for Verilog, with Endpoint capabilities☆127Updated 2 weeks ago
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆117Updated 2 years ago
- SDRAM controller with AXI4 interface☆99Updated 6 years ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆130Updated 3 months ago
- Simple 8-bit UART realization on Verilog HDL.☆111Updated last year
- RISCV model for Verilator/FPGA targets☆53Updated 6 years ago
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆101Updated last month
- Standard Cell Library based Memory Compiler using FF/Latch cells☆162Updated last month
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆68Updated 5 years ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆143Updated 3 weeks ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆73Updated this week
- FTDI FT600 SuperSpeed USB3.0 to AXI bus master☆97Updated 5 years ago
- Verilog wishbone components☆123Updated 2 years ago
- Open source ISS and logic RISC-V 32 bit project☆61Updated 3 weeks ago
- RISC-V System on Chip Template☆159Updated 4 months ago
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆77Updated 5 months ago
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆53Updated 4 years ago
- Basic RISC-V Test SoC☆162Updated 6 years ago