This project offers an immersive tutorial experienced within the context of the Advanced Physical Design, focusing on the utilization of OpenLANE. This repo is the continuity of VLSI ASIC Design Flow
☆43Sep 21, 2023Updated 3 years ago
Alternatives and similar repositories for VLSI-Physical-Design-Flow
Users that are interested in VLSI-Physical-Design-Flow are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- This repository is dedicated to VLSI ASIC Design Flow using open-source tools! Here, we embark on a journey that starts with specificatio…☆57Jan 23, 2024Updated 2 years ago
- This is this VLSI designing Project. This Project is created in Cadence Virtuoso. See the PDF for Pre-Post layout results and other detai…☆49Mar 22, 2019Updated 7 years ago
- RTL Synthesis for Fast Arithmetic circuits like Booth encoded Multipliers, Carry Save Adders, Fixed-Point and Floating-Point conversions,…☆22Nov 26, 2018Updated 7 years ago
- This script builds openlane and all its dependencies on an Ubuntu (only) System.☆26Aug 12, 2022Updated 4 years ago
- The project involves the design of a 4X4 (16-bit) SRAM Memory Array using Cadence Virtuoso☆68Mar 21, 2024Updated 2 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- A Spiking Neuron Network Project in Verilog Implementation☆28Apr 5, 2018Updated 8 years ago
- 2 Week digital VLSI SoC design and planning workshop with complete RTL2GDSII flow organised by VSD in collaboration with NASSCOM (Advance…☆72Apr 13, 2024Updated 2 years ago
- This repository documents my work on Advanced Physical Design Using OpenLANE/Sky130. The objective of this project was to implement an op…☆24Jul 7, 2021Updated 5 years ago
- Open Source VLSI Tools☆33Feb 6, 2021Updated 5 years ago
- A simple VGA monitor simulator to test Verilog models☆18Dec 17, 2023Updated 2 years ago
- ☆16Jun 28, 2021Updated 5 years ago
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆66Jul 9, 2021Updated 5 years ago
- This projects contains Veriolg code and timing analysis of a asynchronous FIFO. The README.md document is maintained, which explains ever…☆51Jul 29, 2024Updated 2 years ago
- ☆18Dec 13, 2022Updated 3 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- This project give overview of RTL to GDSII of universal shift register using OpenLane and Skywater130 PDK. OpenLane is an automated open-…☆11Jul 19, 2022Updated 4 years ago
- This repository contains the tasks performed for VL508- Physical Design of ASIC Course (Fall 2024)☆34Nov 25, 2024Updated last year
- This repository contains all the information included in the beginner SoC/physical design using open-source EDA tools organized by VLSI S…☆14Mar 7, 2021Updated 5 years ago
- Complete ASIC Design of UART Interface with Baud Rate Selection :- RTL to GDS2☆13Sep 3, 2019Updated 7 years ago
- Welcome to the 108 RTL Projects repository! This collection aims to provide a comprehensive set of RTL design projects ranging from simpl…☆64Jan 18, 2025Updated last year
- A simple tool to demonstrate the physical design steps of VLSI Design Flow.☆11Dec 13, 2020Updated 5 years ago
- Memory Compiler Tutorial☆14Oct 7, 2020Updated 5 years ago
- Advanced Integrated Circuits 2025☆14Nov 1, 2025Updated 10 months ago
- NTHU CS6135 VLSI實體設計自動化☆11Mar 12, 2022Updated 4 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Paul Layzell's Evolvable Motherboard☆13Sep 14, 2015Updated 11 years ago
- Education kit for teaching VLSI fundamentals through practical microprocessor design using industry EDA tools (educational)☆366May 30, 2025Updated last year
- Programming assignments for Coursera's U of I VLSI CAD: Logic to Layout☆14May 11, 2014Updated 12 years ago
- eVOLVER Hardware (PCB, 3D printed parts)☆11Jun 25, 2026Updated 3 months ago
- Digital IC design and vlsi notes☆15Jun 24, 2020Updated 6 years ago
- Data Science Foundations: Python Scientific Stack☆11Jun 2, 2022Updated 4 years ago
- VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft the…☆170Apr 1, 2026Updated 5 months ago
- All the projects and assignments done as part of VLSI course.☆21Sep 23, 2020Updated 6 years ago
- midi-controlled synth example for STM32F407VG Discovery board☆14Jul 28, 2021Updated 5 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Implementation of a binary search tree algorithm in a FPGA/ASIC IP☆21Sep 5, 2021Updated 5 years ago
- This repo is "NTHU VLSI System Design and Implementation" course project.☆14Mar 5, 2017Updated 9 years ago
- The template for VLSI project☆27May 10, 2019Updated 7 years ago
- This project is about building a Clocked Comparator to be used in a 4-bit Flash ADC & minimize the ADC Figure of Merit given by FoM = Pow…☆18Sep 12, 2023Updated 3 years ago
- The next generation of OpenLane, rewritten from scratch with a modular architecture☆374Dec 2, 2025Updated 9 months ago
- opensource EDA tool flor VLSI design☆38Sep 17, 2023Updated 3 years ago
- This project shows how to design a clock bootstrapped circuit to improve the nonlinearity of the switch used in Track & Hold circuit. A c…☆13Jul 8, 2019Updated 7 years ago