VardhanSuroshi / VLSI-Physical-Design-FlowLinks
This project offers an immersive tutorial experienced within the context of the Advanced Physical Design, focusing on the utilization of OpenLANE. This repo is the continuity of VLSI ASIC Design Flow
☆21Updated last year
Alternatives and similar repositories for VLSI-Physical-Design-Flow
Users that are interested in VLSI-Physical-Design-Flow are comparing it to the libraries listed below
Sorting:
- ☆42Updated 3 years ago
- This repository is dedicated to VLSI ASIC Design Flow using open-source tools! Here, we embark on a journey that starts with specificatio…☆21Updated last year
- EE 628: Analysis and Design of Integrated Circuits (University of Hawaiʻi at Mānoa)☆164Updated 3 weeks ago
- This script builds openlane and all its dependencies on an Ubuntu (only) System.☆21Updated 3 years ago
- ☆84Updated 7 months ago
- Static Timing Analysis Full Course☆59Updated 2 years ago
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆74Updated 4 years ago
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆65Updated 2 years ago
- Curriculum for a university course to teach chip design using open source EDA tools☆107Updated last year
- ☆100Updated 2 weeks ago
- This project produces a clean GDSII Layout with all its details that are used to print photomasks used in the fabrication of a behavioral…☆14Updated 3 years ago
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.☆75Updated last year
- This repository contains all the contents studied and created during the Advanced Physical Design Workshop using OpenLANE and SKY130 PDK☆42Updated 3 years ago
- The project is about building an 8-row by 8-bit 6T SRAM memory array, & a 3-to-8 decoder that's used to access the SRAM array. The layout…☆75Updated 3 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆76Updated 4 years ago
- ☆15Updated 2 years ago
- This project describes how the PNR of an analog IP, 2:1 analog multiplexer is carried out by opensource EDA tools, Openlane. It also disc…☆44Updated 4 years ago
- The project involves the design of a 4X4 (16-bit) SRAM Memory Array using Cadence Virtuoso☆36Updated last year
- 5 Day TCL begginer to advanced training workshop by VSD☆18Updated last year
- Introductory course into static timing analysis (STA).☆97Updated 2 months ago
- A rudimental RISCV CPU supporting RV32I instructions, in VHDL☆122Updated 4 years ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆112Updated last week
- XSCHEM symbol libraries for the Google-Skywater 130nm process design kit.☆64Updated 2 months ago
- The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…☆27Updated 3 years ago
- A set of Wishbone Controlled SPI Flash Controllers☆88Updated 2 years ago
- Simple strutured VERILOG netlist to SPICE netlist translator☆21Updated 3 years ago
- ☆13Updated 2 years ago
- Repository gathering basic modules for CDC purpose☆54Updated 5 years ago
- This repository documents my work on Advanced Physical Design Using OpenLANE/Sky130. The objective of this project was to implement an op…☆17Updated 4 years ago
- Asynchronous fifo in verilog☆35Updated 9 years ago