librecores / librecores-webLinks
LibreCores Web Site
☆35Updated 2 years ago
Alternatives and similar repositories for librecores-web
Users that are interested in librecores-web are comparing it to the libraries listed below
Sorting:
- Random ideas and interesting ideas for things we hope to eventually do.☆87Updated 3 years ago
- OpenRISC Conference Website☆16Updated 11 months ago
- Open Processor Architecture☆26Updated 9 years ago
- Free open source EDA tools☆66Updated 5 years ago
- ReonV is a modified version of the Leon3, a synthesisable VHDL model of a 32-bit processor originally compliant with the SPARC V8 archite…☆77Updated 2 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆51Updated 3 years ago
- Untethered (stand-alone) FPGA implementation of the lowRISC SoC☆56Updated 5 years ago
- Torc: Tools for Open Reconfigurable Computing☆39Updated 8 years ago
- An online Verilog IDE based on YosysJS.☆24Updated 9 years ago
- ☆113Updated 4 years ago
- Git repository to manage the fixes I need to make to the alliance-5.0-20090901 source for Mac OS X compiles.☆17Updated 14 years ago
- FOSSi Foundation Website☆18Updated 9 months ago
- Firmware infrastructure, contain RTOS Abstraction Layer, demos and more...☆52Updated 3 years ago
- a parallel sorting algorithm implemented in hardware that sorts data in linear time as it arrives serially☆40Updated 9 years ago
- A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems☆43Updated 2 years ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆57Updated 5 years ago
- A 32-bit Microcontroller featuring a RISC-V core☆153Updated 7 years ago
- A 32-bit RISC-V processor for mriscv project☆58Updated 8 years ago
- Copyleftist's Standard Cell Library☆99Updated last year
- Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL☆88Updated 5 years ago
- mirror of https://git.elphel.com/Elphel/vdt-plugin☆15Updated 7 years ago
- A collection of big designs to run post-synthesis simulations with yosys☆49Updated 9 years ago
- Regression test suite for Icarus Verilog. (OBSOLETE)☆115Updated 2 years ago
- Yosys Plugins☆21Updated 6 years ago
- Core description files for FuseSoC☆124Updated 5 years ago
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆34Updated 4 years ago
- Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentaion (Reverse Engineered)☆34Updated 3 years ago
- The 64 bit OpenPOWER Microwatt core, MPW1 tape out☆16Updated 3 years ago
- A Verilog Synthesis Regression Test☆37Updated last year
- A ZipCPU SoC for the Nexys Video board supporting video functionality☆18Updated 8 months ago