smlgit / fpbinary

Related projects: ⓘ

• hgomersall / Ovenbird
  A tool for merging the MyHDL workflow with Vivado
  ☆19Updated 4 years ago
• sgherbst / svreal
  Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats
  ☆42Updated 3 years ago
• Nic30 / hwtLib
  hardware library for hwt (= ipcore repo)
  ☆34Updated 3 months ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆59Updated 2 weeks ago
• antmicro / cocotb-verilator-build
  ☆25Updated last year
• SymbiFlow / sphinxcontrib-hdl-diagrams
  Sphinx Extension which generates various types of diagrams from Verilog code.
  ☆52Updated 11 months ago
• slaclab / ruckus
  Vivado build system
  ☆68Updated last week
• FPHDL / fphdl
  VHDL-2008 Support Library
  ☆54Updated 7 years ago
• suoto / fpga_cores
  ☆32Updated last year
• paulscherrerinstitute / psi_fix
  Fixed-point library with bittrue implementations in VHDL (for FPGA) and python (for simulation)
  ☆22Updated 2 months ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆52Updated last year
• SystemRDL / PeakRDL-regblock
  Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
  ☆48Updated 2 months ago
• Paebbels / pyVHDLParser
  Streaming based VHDL parser.
  ☆77Updated 2 months ago
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆68Updated 2 years ago
• VUnit / tdd-intro
  Example of Test Driven Design with VUnit
  ☆12Updated 2 years ago
• christoph-weiser / mpw6
  submission repository for efabless mpw6 shuttle
  ☆30Updated 8 months ago
• bensampson5 / libsv
  An open source, parameterized SystemVerilog digital hardware IP library
  ☆21Updated 3 months ago
• cirosantilli / vcdvcd
  Python Verilog value change dump (VCD) parser library + the nifty vcdcat VCD command line pretty printer.
  ☆55Updated last month
• rftafas / stdcores
  Standard and Curated cores, tested and working.
  ☆11Updated last year
• SystemRDL / PeakRDL-html
  Generate address space documentation HTML from compiled SystemRDL input
  ☆46Updated 2 weeks ago
• hukenovs / fp23fftk
  Floating point Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source lang. - VHDL).
  ☆53Updated 2 years ago
• ghdl / ghdl-cosim
  Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL
  ☆46Updated this week
• Xilinx / chipscopy
  ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…
  ☆45Updated 3 months ago
• esynr3z / corsair
  Control and Status Register map generator for HDL projects
  ☆96Updated last month
• VHDL / pyVHDLModel
  An abstract language model of VHDL written in Python.
  ☆48Updated 3 weeks ago
• witchard / nbwavedrom
  A simple function to add wavedrom diagrams into an ipython notebook.
  ☆22Updated 2 years ago
• kevinpt / hdlparse
  Simple parser for extracting VHDL documentation
  ☆69Updated 2 months ago
• BerkeleyLab / Bedrock
  LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled
  ☆52Updated 2 weeks ago
• sarafs1926 / ZCU216-PYNQ
  Board repo for the ZCU216 RFSOC
  ☆25Updated 2 years ago
• idea-fasoc / fasoc
  ☆52Updated 11 months ago