Alternatives and similar repositories for sootty

Users that are interested in sootty are comparing it to the libraries listed below

• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆82Updated 3 years ago
• pieter3d / simview
  ☆88Updated 2 months ago
• ics-jku / wal
  WAL enables programmable waveform analysis.
  ☆163Updated last month
• tmeissner / psl_with_ghdl
  Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
  ☆66Updated 10 months ago
• ghdl / ghdl-cosim
  Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL
  ☆51Updated this week
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆181Updated this week
• wyvernSemi / vproc
  Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments
  ☆69Updated 2 months ago
• hdl-registers / hdl-registers
  An open-source HDL register code generator fast enough to run in real time.
  ☆77Updated last week
• sgherbst / svinst
  Determines the modules declared and instantiated in a SystemVerilog file
  ☆49Updated last year
• SymbiFlow / sphinxcontrib-hdl-diagrams
  Sphinx Extension which generates various types of diagrams from Verilog code.
  ☆63Updated 2 years ago
• OSVVM / Documentation
  OSVVM Documentation
  ☆36Updated this week
• fossi-foundation / wishbone
  Specification of the Wishbone SoC Interconnect Architecture
  ☆50Updated 3 years ago
• Intuity / forastero
  Making cocotb testbenches that bit easier
  ☆36Updated last month
• kevinpt / hdlparse
  Simple parser for extracting VHDL documentation
  ☆72Updated last year
• MikePopoloski / pyslang
  Python bindings for slang, a library for compiling SystemVerilog
  ☆65Updated 10 months ago
• MJoergen / formal
  Playing around with Formal Verification of Verilog and VHDL
  ☆64Updated 4 years ago
• AsFigo / pyslint
  SystemVerilog Linter based on pyslang
  ☆31Updated 7 months ago
• cirosantilli / vcdvcd
  Python Verilog value change dump (VCD) parser library + the nifty vcdcat VCD command line pretty printer.
  ☆65Updated last month
• SystemRDL / PeakRDL-html
  Generate address space documentation HTML from compiled SystemRDL input
  ☆58Updated 3 weeks ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆76Updated 4 months ago
• fvutils / pyhdl-if
  Python interface for cross-calling with HDL
  ☆45Updated this week
• Paebbels / pyVHDLParser
  Streaming based VHDL parser.
  ☆84Updated last year
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆60Updated last year
• SystemRDL / PeakRDL
  Control and status register code generator toolchain
  ☆156Updated 2 weeks ago
• hdl / containers
  Building and deploying container images for open source electronic design automation (EDA)
  ☆115Updated last year
• themperek / spicebind
  SpiceBind – spice inside HDL simulator
  ☆56Updated 5 months ago
• OSVVM / OsvvmLibraries
  Start here. Includes all other OSVVM libraries as submodules: Utility, Common, Verification Component, and Script.
  ☆72Updated this week
• ThePerfectComputer / FastWaveBackend
  A Rust VCD parser intended to be the backend of a Waveform Viewer(built using egui) that supports dynamically loaded rust plugins.
  ☆49Updated 11 months ago
• fuad1502 / oombak
  Oombak 🌊 is an interactive SystemVerilog simulator UI that runs on your terminal!
  ☆47Updated 2 months ago
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆120Updated 2 years ago