Ben1152000 / soottyLinks
A command-line tool for displaying vcd waveforms.
☆60Updated last year
Alternatives and similar repositories for sootty
Users that are interested in sootty are comparing it to the libraries listed below
Sorting:
- SystemVerilog frontend for Yosys☆165Updated last week
- Determines the modules declared and instantiated in a SystemVerilog file☆47Updated last year
- ☆86Updated last week
- Python script to transform a VCD file to wavedrom format☆80Updated 3 years ago
- Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL☆50Updated this week
- OSVVM Documentation☆35Updated 2 weeks ago
- A SystemVerilog source file pickler.☆60Updated 11 months ago
- An open-source HDL register code generator fast enough to run in real time.☆73Updated 2 weeks ago
- Python Verilog value change dump (VCD) parser library + the nifty vcdcat VCD command line pretty printer.☆62Updated last week
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆119Updated 2 years ago
- Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)☆66Updated 8 months ago
- Sphinx Extension which generates various types of diagrams from Verilog code.☆61Updated 2 years ago
- WAL enables programmable waveform analysis.☆157Updated 4 months ago
- Building and deploying container images for open source electronic design automation (EDA)☆116Updated last year
- SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!☆79Updated 11 months ago
- Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments☆65Updated this week
- A Rust VCD parser intended to be the backend of a Waveform Viewer(built using egui) that supports dynamically loaded rust plugins.☆48Updated 9 months ago
- An automatic clock gating utility☆50Updated 5 months ago
- Test dashboard for verification features in Verilator☆27Updated this week
- Python bindings for slang, a library for compiling SystemVerilog☆63Updated 8 months ago
- Specification of the Wishbone SoC Interconnect Architecture☆46Updated 3 years ago
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆75Updated 2 months ago
- SystemVerilog grammar for tree-sitter☆108Updated 10 months ago
- Simple parser for extracting VHDL documentation☆72Updated last year
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API. Compiles on Li…☆26Updated 3 weeks ago
- ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…☆60Updated 2 months ago
- SpiceBind – spice inside HDL simulator☆55Updated 3 months ago
- Making cocotb testbenches that bit easier☆36Updated this week
- Start here. Includes all other OSVVM libraries as submodules: Utility, Common, Verification Component, and Script.☆67Updated this week
- Limited python / cocotb interface to Xilinx/AMD Vivado simulator.☆61Updated last week