A command-line tool for displaying vcd waveforms.
☆67Feb 19, 2024Updated 2 years ago
Alternatives and similar repositories for sootty
Users that are interested in sootty are comparing it to the libraries listed below
Sorting:
- ☆91Oct 13, 2025Updated 4 months ago
- VCD visualizer: view your waveforms in ASCII format, or export them to TikZ figures.☆32Nov 2, 2025Updated 4 months ago
- impulse is an event and waveform visualization and analysis workbench (simulation, traces, logs) which helps engineers to comfortably und…☆29Dec 1, 2025Updated 3 months ago
- Set up your GitHub Actions workflow with a OSS CAD Suite☆16Mar 21, 2024Updated last year
- A repository that implements Tywaves: enabling a type-based waveform debugging for Chisel and Tydi-Chisel. Mapping from Chisel level code…☆58Oct 27, 2024Updated last year
- Tool to parse yosys and nextpnr logfiles to then plot LUT, flip-flop and maximum frequency stats as your project progresses.☆22Oct 24, 2023Updated 2 years ago
- Python library for operations with VCD and other digital wave files☆55Nov 12, 2025Updated 3 months ago
- PSSGen: Portable Test and Stimulus Standard DSL Generator☆14Dec 29, 2025Updated 2 months ago
- Python script to transform a VCD file to wavedrom format☆84Aug 18, 2022Updated 3 years ago
- VCD file (Value Change Dump) command line viewer☆120Nov 9, 2025Updated 4 months ago
- Verilog AST☆21Dec 2, 2023Updated 2 years ago
- ☆19Feb 12, 2026Updated 3 weeks ago
- sample VCD files☆43Feb 13, 2026Updated 3 weeks ago
- GHDL C extensions☆11Feb 20, 2020Updated 6 years ago
- WaveDrom compatible python command line☆113Jun 2, 2023Updated 2 years ago
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆252Feb 22, 2026Updated 2 weeks ago
- Hardware generator debugger☆77Feb 12, 2024Updated 2 years ago
- SystemVerilog RTL and UVM RAL model generators for RgGen☆17Jan 7, 2026Updated 2 months ago
- 🇯 JSON encoder and decoder in pure SystemVerilog☆14Jul 7, 2024Updated last year
- Simple UVM environment for experimenting with Verilator.☆37Updated this week
- A Rust VCD parser intended to be the backend of a Waveform Viewer(built using egui) that supports dynamically loaded rust plugins.☆50Dec 30, 2024Updated last year
- SystemVerilog parser library fully compliant with IEEE 1800-2017☆464Nov 4, 2025Updated 4 months ago
- softfloat and softposit in Python☆15Aug 2, 2019Updated 6 years ago
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆450Mar 2, 2026Updated last week
- Python package for writing Value Change Dump (VCD) files.☆131Nov 10, 2024Updated last year
- Prefix tree adder space exploration library☆56Jan 27, 2026Updated last month
- This is an OOT module for GNU Radio integrating verilog simulation feature☆38Sep 23, 2019Updated 6 years ago
- Cross EDA Abstraction and Automation☆41Nov 17, 2025Updated 3 months ago
- VCD (Value Change Dump) Tracing for C++☆14Mar 1, 2026Updated last week
- Generate address space documentation HTML from compiled SystemRDL input☆61Updated this week
- assorted library of utility cores for amaranth HDL☆102Sep 17, 2024Updated last year
- Python packages providing a library for Verification Stimulus and Coverage☆141Feb 18, 2026Updated 2 weeks ago
- A tiny Python package to parse spice raw data files.☆53Dec 26, 2022Updated 3 years ago
- CLI for WaveDrom☆68Feb 22, 2024Updated 2 years ago
- Debuggable hardware generator☆71Feb 17, 2023Updated 3 years ago
- Custom IC Creator (ciccreator) is a compiler that takes in a object definition file (JSON), a SPICE file, and a design rule file and outp…☆34Jun 22, 2025Updated 8 months ago
- command line tool for frequent amaranth HDL tasks (generate sources, show design)☆17Dec 27, 2021Updated 4 years ago
- HTML & Js based VCD viewer☆72Feb 16, 2026Updated 3 weeks ago
- iCE40 floorplan viewer☆24Jun 23, 2018Updated 7 years ago