Ben1152000 / soottyLinks
A command-line tool for displaying vcd waveforms.
☆59Updated last year
Alternatives and similar repositories for sootty
Users that are interested in sootty are comparing it to the libraries listed below
Sorting:
- SystemVerilog frontend for Yosys☆128Updated this week
- A Rust VCD parser intended to be the backend of a Waveform Viewer(built using egui) that supports dynamically loaded rust plugins.☆44Updated 5 months ago
- Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)☆66Updated 4 months ago
- Python script to transform a VCD file to wavedrom format☆77Updated 2 years ago
- OSVVM Documentation☆34Updated this week
- A SystemVerilog source file pickler.☆57Updated 8 months ago
- An automatic clock gating utility☆49Updated 2 months ago
- Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL☆48Updated this week
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆70Updated 9 months ago
- Determines the modules declared and instantiated in a SystemVerilog file☆44Updated 9 months ago
- An open-source HDL register code generator fast enough to run in real time.☆71Updated this week
- Prefix tree adder space exploration library☆57Updated 7 months ago
- SystemVerilog Linter based on pyslang☆31Updated last month
- Open Source Verification Bundle for VHDL and System Verilog☆45Updated last year
- Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments☆62Updated 3 weeks ago
- ☆36Updated 2 years ago
- ☆79Updated last year
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆114Updated last year
- RISC-V Nox core☆64Updated 3 months ago
- Python bindings for slang, a library for compiling SystemVerilog☆59Updated 5 months ago
- Making cocotb testbenches that bit easier☆33Updated last week
- Playing around with Formal Verification of Verilog and VHDL☆58Updated 4 years ago
- ☆46Updated 2 months ago
- Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.☆67Updated this week
- Specification of the Wishbone SoC Interconnect Architecture☆45Updated 3 years ago
- WAL enables programmable waveform analysis.☆154Updated 2 weeks ago
- Start here. Includes all other OSVVM libraries as submodules: Utility, Common, Verification Component, and Script.☆64Updated this week
- ☆31Updated last year
- ☆32Updated 5 months ago
- ☆23Updated this week